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-rw-r--r--src/VeriFuzz/Verilog/AST.hs21
-rw-r--r--src/VeriFuzz/Verilog/CodeGen.hs16
-rw-r--r--src/VeriFuzz/Verilog/Eval.hs6
-rw-r--r--src/VeriFuzz/Verilog/Gen.hs23
-rw-r--r--src/VeriFuzz/Verilog/Internal.hs2
-rw-r--r--src/VeriFuzz/Verilog/Mutate.hs60
-rw-r--r--src/VeriFuzz/Verilog/Parser.hs23
-rw-r--r--src/VeriFuzz/Verilog/Quote.hs4
8 files changed, 86 insertions, 69 deletions
diff --git a/src/VeriFuzz/Verilog/AST.hs b/src/VeriFuzz/Verilog/AST.hs
index 306366c..43063e6 100644
--- a/src/VeriFuzz/Verilog/AST.hs
+++ b/src/VeriFuzz/Verilog/AST.hs
@@ -139,14 +139,18 @@ module VeriFuzz.Verilog.AST
)
where
-import Control.Lens hiding ((<|))
+import Control.Lens hiding ( (<|) )
import Data.Data
import Data.Data.Lens
-import Data.Functor.Foldable.TH (makeBaseFunctor)
-import Data.List.NonEmpty (NonEmpty (..), (<|))
-import Data.String (IsString, fromString)
-import Data.Text (Text)
-import Data.Traversable (sequenceA)
+import Data.Functor.Foldable.TH ( makeBaseFunctor )
+import Data.List.NonEmpty ( NonEmpty(..)
+ , (<|)
+ )
+import Data.String ( IsString
+ , fromString
+ )
+import Data.Text ( Text )
+import Data.Traversable ( sequenceA )
import VeriFuzz.Verilog.BitVec
-- | Identifier in Verilog. This is just a string of characters that can either
@@ -169,6 +173,9 @@ data Event = EId {-# UNPACK #-} !Identifier
| EComb !Event !Event
deriving (Eq, Show, Ord, Data)
+instance Plated Event where
+ plate = uniplate
+
-- | Binary operators that are currently supported in the verilog generation.
data BinaryOperator = BinPlus -- ^ @+@
| BinMinus -- ^ @-@
@@ -492,7 +499,7 @@ newtype Verilog = Verilog { getVerilog :: [ModDecl] }
data SourceInfo = SourceInfo { _infoTop :: {-# UNPACK #-} !Text
, _infoSrc :: !Verilog
}
- deriving (Eq, Show)
+ deriving (Eq, Ord, Data, Show)
$(makeLenses ''Expr)
$(makeLenses ''ConstExpr)
diff --git a/src/VeriFuzz/Verilog/CodeGen.hs b/src/VeriFuzz/Verilog/CodeGen.hs
index a0ec0cc..82945aa 100644
--- a/src/VeriFuzz/Verilog/CodeGen.hs
+++ b/src/VeriFuzz/Verilog/CodeGen.hs
@@ -17,18 +17,20 @@ This module generates the code from the Verilog AST defined in
module VeriFuzz.Verilog.CodeGen
( -- * Code Generation
GenVerilog(..)
- , genSource
+ , Source(..)
, render
)
where
-import Data.Data (Data)
-import Data.List.NonEmpty (NonEmpty (..), toList)
-import Data.Text (Text)
-import qualified Data.Text as T
+import Data.Data ( Data )
+import Data.List.NonEmpty ( NonEmpty(..)
+ , toList
+ )
+import Data.Text ( Text )
+import qualified Data.Text as T
import Data.Text.Prettyprint.Doc
-import Numeric (showHex)
-import VeriFuzz.Internal hiding (comma)
+import Numeric ( showHex )
+import VeriFuzz.Internal hiding ( comma )
import VeriFuzz.Verilog.AST
import VeriFuzz.Verilog.BitVec
diff --git a/src/VeriFuzz/Verilog/Eval.hs b/src/VeriFuzz/Verilog/Eval.hs
index 4a43c19..d8840e3 100644
--- a/src/VeriFuzz/Verilog/Eval.hs
+++ b/src/VeriFuzz/Verilog/Eval.hs
@@ -17,9 +17,9 @@ module VeriFuzz.Verilog.Eval
where
import Data.Bits
-import Data.Foldable (fold)
-import Data.Functor.Foldable hiding (fold)
-import Data.Maybe (listToMaybe)
+import Data.Foldable ( fold )
+import Data.Functor.Foldable hiding ( fold )
+import Data.Maybe ( listToMaybe )
import VeriFuzz.Verilog.AST
import VeriFuzz.Verilog.BitVec
diff --git a/src/VeriFuzz/Verilog/Gen.hs b/src/VeriFuzz/Verilog/Gen.hs
index f2d2b0a..f08e5a6 100644
--- a/src/VeriFuzz/Verilog/Gen.hs
+++ b/src/VeriFuzz/Verilog/Gen.hs
@@ -237,14 +237,6 @@ someI m f = do
amount <- gen $ Hog.int (Hog.linear 1 m)
replicateM amount f
-some :: StateGen a -> StateGen [a]
-some = someI 50
-
-many :: StateGen a -> StateGen [a]
-many f = do
- amount <- gen $ Hog.int (Hog.linear 0 50)
- replicateM amount f
-
makeIdentifier :: T.Text -> StateGen Identifier
makeIdentifier prefix = do
context <- get
@@ -481,10 +473,11 @@ calcRange ps i (Range l r) = eval l - eval r + 1
moduleDef :: Maybe Identifier -> StateGen ModDecl
moduleDef top = do
name <- moduleName top
- portList <- some $ nextPort Wire
+ portList <- Hog.list (Hog.linear 4 10) $ nextPort Wire
mi <- Hog.list (Hog.linear 4 100) modItem
- ps <- many parameter
+ ps <- Hog.list (Hog.linear 0 10) parameter
context <- get
+ config <- lift ask
let local = filter (`notElem` portList) $ _variables context
let
size =
@@ -493,12 +486,14 @@ moduleDef top = do
$ local
^.. traverse
. portSize
- let clock = Port Wire False 1 "clk"
- let yport = Port Wire False size "y"
- let comb = combineAssigns_ yport local
+ let combine = config ^. configProperty . propCombine
+ let clock = Port Wire False 1 "clk"
+ let yport =
+ if combine then Port Wire False 1 "y" else Port Wire False size "y"
+ let comb = combineAssigns_ combine yport local
return
. declareMod local
- . ModDecl name [yport] (clock : portList) (mi <> [comb])
+ . ModDecl name [yport] (clock : portList) (comb : mi)
$ ps
-- | Procedural generation method for random Verilog. Uses internal 'Reader' and
diff --git a/src/VeriFuzz/Verilog/Internal.hs b/src/VeriFuzz/Verilog/Internal.hs
index 8d19c14..16148cf 100644
--- a/src/VeriFuzz/Verilog/Internal.hs
+++ b/src/VeriFuzz/Verilog/Internal.hs
@@ -29,7 +29,7 @@ module VeriFuzz.Verilog.Internal
where
import Control.Lens
-import Data.Text (Text)
+import Data.Text ( Text )
import VeriFuzz.Verilog.AST
regDecl :: Identifier -> ModItem
diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs
index 66f3c37..e4a10df 100644
--- a/src/VeriFuzz/Verilog/Mutate.hs
+++ b/src/VeriFuzz/Verilog/Mutate.hs
@@ -41,10 +41,12 @@ module VeriFuzz.Verilog.Mutate
where
import Control.Lens
-import Data.Foldable (fold)
-import Data.Maybe (catMaybes, fromMaybe)
-import Data.Text (Text)
-import qualified Data.Text as T
+import Data.Foldable ( fold )
+import Data.Maybe ( catMaybes
+ , fromMaybe
+ )
+import Data.Text ( Text )
+import qualified Data.Text as T
import VeriFuzz.Circuit.Internal
import VeriFuzz.Internal
import VeriFuzz.Verilog.AST
@@ -337,30 +339,30 @@ declareMod ports = initMod . (modItems %~ (decl ++))
-- >>> GenVerilog . simplify $ (Id "y") + (Id "x")
-- (y + x)
simplify :: Expr -> Expr
-simplify (BinOp (Number (BitVec _ 1)) BinAnd e) = e
-simplify (BinOp e BinAnd (Number (BitVec _ 1))) = e
-simplify (BinOp (Number (BitVec _ 0)) BinAnd _) = Number 0
-simplify (BinOp _ BinAnd (Number (BitVec _ 0))) = Number 0
-simplify (BinOp e BinPlus (Number (BitVec _ 0))) = e
-simplify (BinOp (Number (BitVec _ 0)) BinPlus e) = e
+simplify (BinOp (Number (BitVec _ 1)) BinAnd e) = e
+simplify (BinOp e BinAnd (Number (BitVec _ 1))) = e
+simplify (BinOp (Number (BitVec _ 0)) BinAnd _) = Number 0
+simplify (BinOp _ BinAnd (Number (BitVec _ 0))) = Number 0
+simplify (BinOp e BinPlus (Number (BitVec _ 0))) = e
+simplify (BinOp (Number (BitVec _ 0)) BinPlus e) = e
simplify (BinOp e BinMinus (Number (BitVec _ 0))) = e
simplify (BinOp (Number (BitVec _ 0)) BinMinus e) = e
simplify (BinOp e BinTimes (Number (BitVec _ 1))) = e
simplify (BinOp (Number (BitVec _ 1)) BinTimes e) = e
simplify (BinOp _ BinTimes (Number (BitVec _ 0))) = Number 0
simplify (BinOp (Number (BitVec _ 0)) BinTimes _) = Number 0
-simplify (BinOp e BinOr (Number (BitVec _ 0))) = e
-simplify (BinOp (Number (BitVec _ 0)) BinOr e) = e
-simplify (BinOp e BinLSL (Number (BitVec _ 0))) = e
-simplify (BinOp (Number (BitVec _ 0)) BinLSL e) = e
-simplify (BinOp e BinLSR (Number (BitVec _ 0))) = e
-simplify (BinOp (Number (BitVec _ 0)) BinLSR e) = e
-simplify (BinOp e BinASL (Number (BitVec _ 0))) = e
-simplify (BinOp (Number (BitVec _ 0)) BinASL e) = e
-simplify (BinOp e BinASR (Number (BitVec _ 0))) = e
-simplify (BinOp (Number (BitVec _ 0)) BinASR e) = e
-simplify (UnOp UnPlus e) = e
-simplify e = e
+simplify (BinOp e BinOr (Number (BitVec _ 0))) = e
+simplify (BinOp (Number (BitVec _ 0)) BinOr e) = e
+simplify (BinOp e BinLSL (Number (BitVec _ 0))) = e
+simplify (BinOp (Number (BitVec _ 0)) BinLSL e) = e
+simplify (BinOp e BinLSR (Number (BitVec _ 0))) = e
+simplify (BinOp (Number (BitVec _ 0)) BinLSR e) = e
+simplify (BinOp e BinASL (Number (BitVec _ 0))) = e
+simplify (BinOp (Number (BitVec _ 0)) BinASL e) = e
+simplify (BinOp e BinASR (Number (BitVec _ 0))) = e
+simplify (BinOp (Number (BitVec _ 0)) BinASR e) = e
+simplify (UnOp UnPlus e) = e
+simplify e = e
-- | Remove all 'Identifier' that do not appeare in the input list from an
-- 'Expr'. The identifier will be replaced by @1'b0@, which can then later be
@@ -377,13 +379,21 @@ removeId i = transform trans
combineAssigns :: Port -> [ModItem] -> [ModItem]
combineAssigns p a =
- a <> [ModCA . ContAssign (p ^. portName) . fold $ Id <$> assigns]
+ a
+ <> [ ModCA
+ . ContAssign (p ^. portName)
+ . UnOp UnXor
+ . fold
+ $ Id
+ <$> assigns
+ ]
where assigns = a ^.. traverse . modContAssign . contAssignNetLVal
-combineAssigns_ :: Port -> [Port] -> ModItem
-combineAssigns_ p ps =
+combineAssigns_ :: Bool -> Port -> [Port] -> ModItem
+combineAssigns_ comb p ps =
ModCA
. ContAssign (p ^. portName)
+ . (if comb then UnOp UnXor else id)
. fold
$ Id
<$> ps
diff --git a/src/VeriFuzz/Verilog/Parser.hs b/src/VeriFuzz/Verilog/Parser.hs
index 68d0ef3..0820e48 100644
--- a/src/VeriFuzz/Verilog/Parser.hs
+++ b/src/VeriFuzz/Verilog/Parser.hs
@@ -26,17 +26,20 @@ module VeriFuzz.Verilog.Parser
where
import Control.Lens
-import Control.Monad (void)
-import Data.Bifunctor (bimap)
+import Control.Monad ( void )
+import Data.Bifunctor ( bimap )
import Data.Bits
-import Data.Functor (($>))
-import Data.Functor.Identity (Identity)
-import Data.List (isInfixOf, isPrefixOf, null)
-import Data.List.NonEmpty (NonEmpty (..))
-import Data.Text (Text)
-import qualified Data.Text as T
-import qualified Data.Text.IO as T
-import Text.Parsec hiding (satisfy)
+import Data.Functor ( ($>) )
+import Data.Functor.Identity ( Identity )
+import Data.List ( isInfixOf
+ , isPrefixOf
+ , null
+ )
+import Data.List.NonEmpty ( NonEmpty(..) )
+import Data.Text ( Text )
+import qualified Data.Text as T
+import qualified Data.Text.IO as T
+import Text.Parsec hiding ( satisfy )
import Text.Parsec.Expr
import VeriFuzz.Internal
import VeriFuzz.Verilog.AST
diff --git a/src/VeriFuzz/Verilog/Quote.hs b/src/VeriFuzz/Verilog/Quote.hs
index 362cf06..f0b7c96 100644
--- a/src/VeriFuzz/Verilog/Quote.hs
+++ b/src/VeriFuzz/Verilog/Quote.hs
@@ -18,8 +18,8 @@ module VeriFuzz.Verilog.Quote
where
import Data.Data
-import qualified Data.Text as T
-import qualified Language.Haskell.TH as TH
+import qualified Data.Text as T
+import qualified Language.Haskell.TH as TH
import Language.Haskell.TH.Quote
import Language.Haskell.TH.Syntax
import VeriFuzz.Verilog.Parser
generated by cgit (git 2.34.1) at 2024-06-26 00:54:14 +0000