diff options
Diffstat (limited to 'src/VeriFuzz/Verilog')
| -rw-r--r-- | src/VeriFuzz/Verilog/Gen.hs | 9 | ||||
| -rw-r--r-- | src/VeriFuzz/Verilog/Mutate.hs | 9 |
2 files changed, 13 insertions, 5 deletions
diff --git a/src/VeriFuzz/Verilog/Gen.hs b/src/VeriFuzz/Verilog/Gen.hs index c8860ce..e52a158 100644 --- a/src/VeriFuzz/Verilog/Gen.hs +++ b/src/VeriFuzz/Verilog/Gen.hs @@ -455,7 +455,7 @@ moduleDef top = do mi <- Hog.list (Hog.linear 4 100) modItem ps <- Hog.list (Hog.linear 0 10) parameter context <- get - config <- lift ask + config <- lift ask let local = filter (`notElem` portList) $ _variables context let size = @@ -465,9 +465,10 @@ moduleDef top = do ^.. traverse . portSize let combine = config ^. configProperty . propCombine - let clock = Port Wire False 1 "clk" - let yport = if combine then Port Wire False 1 "y" else Port Wire False size "y" - let comb = combineAssigns_ combine yport local + let clock = Port Wire False 1 "clk" + let yport = + if combine then Port Wire False 1 "y" else Port Wire False size "y" + let comb = combineAssigns_ combine yport local return . declareMod local . ModDecl name [yport] (clock : portList) (comb : mi) diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs index 7496935..0fb4c49 100644 --- a/src/VeriFuzz/Verilog/Mutate.hs +++ b/src/VeriFuzz/Verilog/Mutate.hs @@ -377,7 +377,14 @@ removeId i = transform trans combineAssigns :: Port -> [ModItem] -> [ModItem] combineAssigns p a = - a <> [ModCA . ContAssign (p ^. portName) . UnOp UnXor . fold $ Id <$> assigns] + a + <> [ ModCA + . ContAssign (p ^. portName) + . UnOp UnXor + . fold + $ Id + <$> assigns + ] where assigns = a ^.. traverse . modContAssign . contAssignNetLVal combineAssigns_ :: Bool -> Port -> [Port] -> ModItem |