diff options
Diffstat (limited to 'src/VeriFuzz/Verilog')
| -rw-r--r-- | src/VeriFuzz/Verilog/Gen.hs | 3 | ||||
| -rw-r--r-- | src/VeriFuzz/Verilog/Mutate.hs | 6 |
2 files changed, 5 insertions, 4 deletions
diff --git a/src/VeriFuzz/Verilog/Gen.hs b/src/VeriFuzz/Verilog/Gen.hs index c903e28..cb3a8ad 100644 --- a/src/VeriFuzz/Verilog/Gen.hs +++ b/src/VeriFuzz/Verilog/Gen.hs @@ -455,6 +455,7 @@ moduleDef top = do mi <- Hog.list (Hog.linear 4 100) modItem ps <- Hog.list (Hog.linear 0 10) parameter context <- get + config <- lift ask let local = filter (`notElem` portList) $ _variables context let size = @@ -465,7 +466,7 @@ moduleDef top = do . portSize let clock = Port Wire False 1 "clk" let yport = if True then Port Wire False 1 "y" else Port Wire False size "y" - let comb = combineAssigns_ yport local + let comb = combineAssigns_ (config ^. configProperty . propCombine) yport local return . declareMod local . ModDecl name [yport] (clock : portList) (comb : mi) diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs index 8af0182..7496935 100644 --- a/src/VeriFuzz/Verilog/Mutate.hs +++ b/src/VeriFuzz/Verilog/Mutate.hs @@ -380,11 +380,11 @@ combineAssigns p a = a <> [ModCA . ContAssign (p ^. portName) . UnOp UnXor . fold $ Id <$> assigns] where assigns = a ^.. traverse . modContAssign . contAssignNetLVal -combineAssigns_ :: Port -> [Port] -> ModItem -combineAssigns_ p ps = +combineAssigns_ :: Bool -> Port -> [Port] -> ModItem +combineAssigns_ comb p ps = ModCA . ContAssign (p ^. portName) - . UnOp UnXor + . (if comb then UnOp UnXor else id) . fold $ Id <$> ps |