diff options
Diffstat (limited to 'src/VeriFuzz/Verilog')
| -rw-r--r-- | src/VeriFuzz/Verilog/AST.hs | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/VeriFuzz/Verilog/AST.hs b/src/VeriFuzz/Verilog/AST.hs index c8d85e6..306366c 100644 --- a/src/VeriFuzz/Verilog/AST.hs +++ b/src/VeriFuzz/Verilog/AST.hs @@ -129,7 +129,6 @@ module VeriFuzz.Verilog.AST , declPort , declVal , ModConn(..) - , modConn , modConnName , modExpr -- * Useful Lenses and Traversals @@ -388,7 +387,7 @@ data Port = Port { _portType :: !PortType -- @ -- mod a(.y(y1), .x1(x11), .x2(x22)); -- @ -data ModConn = ModConn { _modConn :: !Expr } +data ModConn = ModConn { _modExpr :: !Expr } | ModConnNamed { _modConnName :: {-# UNPACK #-} !Identifier , _modExpr :: !Expr } @@ -536,7 +535,8 @@ aModule t = lens get_ set_ SourceInfo top (main & getModule %~ update (getIdentifier t) v) update top v m@(ModDecl (Identifier i) _ _ _ _) | i == top = v | otherwise = m - get_ (SourceInfo _ main) = head . filter (f $ getIdentifier t) $ main ^.. getModule + get_ (SourceInfo _ main) = + head . filter (f $ getIdentifier t) $ main ^.. getModule f top (ModDecl (Identifier i) _ _ _ _) = i == top |