diff options
Diffstat (limited to 'src/VeriFuzz/Verilog')
-rw-r--r-- | src/VeriFuzz/Verilog/CodeGen.hs | 5 | ||||
-rw-r--r-- | src/VeriFuzz/Verilog/Mutate.hs | 4 |
2 files changed, 8 insertions, 1 deletions
diff --git a/src/VeriFuzz/Verilog/CodeGen.hs b/src/VeriFuzz/Verilog/CodeGen.hs index efacd3c..71ba162 100644 --- a/src/VeriFuzz/Verilog/CodeGen.hs +++ b/src/VeriFuzz/Verilog/CodeGen.hs @@ -11,7 +11,8 @@ This module generates the code from the Verilog AST defined in "VeriFuzz.Verilog.AST". -} -{-# LANGUAGE FlexibleInstances #-} +{-# LANGUAGE DeriveDataTypeable #-} +{-# LANGUAGE FlexibleInstances #-} module VeriFuzz.Verilog.CodeGen ( -- * Code Generation @@ -21,6 +22,7 @@ module VeriFuzz.Verilog.CodeGen ) where +import Data.Data (Data) import Data.List.NonEmpty (NonEmpty (..), toList) import Data.Text (Text) import qualified Data.Text as T @@ -318,6 +320,7 @@ instance Source SourceInfo where genSource (SourceInfo _ src) = genSource src newtype GenVerilog a = GenVerilog { unGenVerilog :: a } + deriving (Eq, Ord, Data) instance (Source a) => Show (GenVerilog a) where show = T.unpack . genSource . unGenVerilog diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs index 3f0ae83..66f3c37 100644 --- a/src/VeriFuzz/Verilog/Mutate.hs +++ b/src/VeriFuzz/Verilog/Mutate.hs @@ -49,6 +49,7 @@ import VeriFuzz.Circuit.Internal import VeriFuzz.Internal import VeriFuzz.Verilog.AST import VeriFuzz.Verilog.BitVec +import VeriFuzz.Verilog.CodeGen import VeriFuzz.Verilog.Internal class Mutate a where @@ -146,6 +147,9 @@ instance Mutate a => Mutate [a] where instance Mutate a => Mutate (Maybe a) where mutExpr f a = mutExpr f <$> a +instance Mutate a => Mutate (GenVerilog a) where + mutExpr f (GenVerilog a) = GenVerilog $ mutExpr f a + -- | Return if the 'Identifier' is in a 'ModDecl'. inPort :: Identifier -> ModDecl -> Bool inPort i m = inInput |