diff options
Diffstat (limited to 'src/VeriFuzz/Verilog')
-rw-r--r-- | src/VeriFuzz/Verilog/AST.hs | 16 | ||||
-rw-r--r-- | src/VeriFuzz/Verilog/CodeGen.hs | 14 | ||||
-rw-r--r-- | src/VeriFuzz/Verilog/Eval.hs | 6 | ||||
-rw-r--r-- | src/VeriFuzz/Verilog/Gen.hs | 21 | ||||
-rw-r--r-- | src/VeriFuzz/Verilog/Internal.hs | 2 | ||||
-rw-r--r-- | src/VeriFuzz/Verilog/Mutate.hs | 46 | ||||
-rw-r--r-- | src/VeriFuzz/Verilog/Parser.hs | 23 | ||||
-rw-r--r-- | src/VeriFuzz/Verilog/Quote.hs | 4 |
8 files changed, 72 insertions, 60 deletions
diff --git a/src/VeriFuzz/Verilog/AST.hs b/src/VeriFuzz/Verilog/AST.hs index f201064..43063e6 100644 --- a/src/VeriFuzz/Verilog/AST.hs +++ b/src/VeriFuzz/Verilog/AST.hs @@ -139,14 +139,18 @@ module VeriFuzz.Verilog.AST ) where -import Control.Lens hiding ((<|)) +import Control.Lens hiding ( (<|) ) import Data.Data import Data.Data.Lens -import Data.Functor.Foldable.TH (makeBaseFunctor) -import Data.List.NonEmpty (NonEmpty (..), (<|)) -import Data.String (IsString, fromString) -import Data.Text (Text) -import Data.Traversable (sequenceA) +import Data.Functor.Foldable.TH ( makeBaseFunctor ) +import Data.List.NonEmpty ( NonEmpty(..) + , (<|) + ) +import Data.String ( IsString + , fromString + ) +import Data.Text ( Text ) +import Data.Traversable ( sequenceA ) import VeriFuzz.Verilog.BitVec -- | Identifier in Verilog. This is just a string of characters that can either diff --git a/src/VeriFuzz/Verilog/CodeGen.hs b/src/VeriFuzz/Verilog/CodeGen.hs index 6ef1959..82945aa 100644 --- a/src/VeriFuzz/Verilog/CodeGen.hs +++ b/src/VeriFuzz/Verilog/CodeGen.hs @@ -22,13 +22,15 @@ module VeriFuzz.Verilog.CodeGen ) where -import Data.Data (Data) -import Data.List.NonEmpty (NonEmpty (..), toList) -import Data.Text (Text) -import qualified Data.Text as T +import Data.Data ( Data ) +import Data.List.NonEmpty ( NonEmpty(..) + , toList + ) +import Data.Text ( Text ) +import qualified Data.Text as T import Data.Text.Prettyprint.Doc -import Numeric (showHex) -import VeriFuzz.Internal hiding (comma) +import Numeric ( showHex ) +import VeriFuzz.Internal hiding ( comma ) import VeriFuzz.Verilog.AST import VeriFuzz.Verilog.BitVec diff --git a/src/VeriFuzz/Verilog/Eval.hs b/src/VeriFuzz/Verilog/Eval.hs index 4a43c19..d8840e3 100644 --- a/src/VeriFuzz/Verilog/Eval.hs +++ b/src/VeriFuzz/Verilog/Eval.hs @@ -17,9 +17,9 @@ module VeriFuzz.Verilog.Eval where import Data.Bits -import Data.Foldable (fold) -import Data.Functor.Foldable hiding (fold) -import Data.Maybe (listToMaybe) +import Data.Foldable ( fold ) +import Data.Functor.Foldable hiding ( fold ) +import Data.Maybe ( listToMaybe ) import VeriFuzz.Verilog.AST import VeriFuzz.Verilog.BitVec diff --git a/src/VeriFuzz/Verilog/Gen.hs b/src/VeriFuzz/Verilog/Gen.hs index e52a158..0a6ece5 100644 --- a/src/VeriFuzz/Verilog/Gen.hs +++ b/src/VeriFuzz/Verilog/Gen.hs @@ -22,17 +22,18 @@ module VeriFuzz.Verilog.Gen ) where -import Control.Lens hiding (Context) -import Control.Monad (replicateM) -import Control.Monad.Trans.Class (lift) -import Control.Monad.Trans.Reader hiding (local) +import Control.Lens hiding ( Context ) +import Control.Monad ( replicateM ) +import Control.Monad.Trans.Class ( lift ) +import Control.Monad.Trans.Reader + hiding ( local ) import Control.Monad.Trans.State.Strict -import Data.Foldable (fold) -import Data.Functor.Foldable (cata) -import qualified Data.Text as T -import Hedgehog (Gen) -import qualified Hedgehog.Gen as Hog -import qualified Hedgehog.Range as Hog +import Data.Foldable ( fold ) +import Data.Functor.Foldable ( cata ) +import qualified Data.Text as T +import Hedgehog ( Gen ) +import qualified Hedgehog.Gen as Hog +import qualified Hedgehog.Range as Hog import VeriFuzz.Config import VeriFuzz.Internal import VeriFuzz.Verilog.AST diff --git a/src/VeriFuzz/Verilog/Internal.hs b/src/VeriFuzz/Verilog/Internal.hs index 8d19c14..16148cf 100644 --- a/src/VeriFuzz/Verilog/Internal.hs +++ b/src/VeriFuzz/Verilog/Internal.hs @@ -29,7 +29,7 @@ module VeriFuzz.Verilog.Internal where import Control.Lens -import Data.Text (Text) +import Data.Text ( Text ) import VeriFuzz.Verilog.AST regDecl :: Identifier -> ModItem diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs index 0fb4c49..e4a10df 100644 --- a/src/VeriFuzz/Verilog/Mutate.hs +++ b/src/VeriFuzz/Verilog/Mutate.hs @@ -41,10 +41,12 @@ module VeriFuzz.Verilog.Mutate where import Control.Lens -import Data.Foldable (fold) -import Data.Maybe (catMaybes, fromMaybe) -import Data.Text (Text) -import qualified Data.Text as T +import Data.Foldable ( fold ) +import Data.Maybe ( catMaybes + , fromMaybe + ) +import Data.Text ( Text ) +import qualified Data.Text as T import VeriFuzz.Circuit.Internal import VeriFuzz.Internal import VeriFuzz.Verilog.AST @@ -337,30 +339,30 @@ declareMod ports = initMod . (modItems %~ (decl ++)) -- >>> GenVerilog . simplify $ (Id "y") + (Id "x") -- (y + x) simplify :: Expr -> Expr -simplify (BinOp (Number (BitVec _ 1)) BinAnd e) = e -simplify (BinOp e BinAnd (Number (BitVec _ 1))) = e -simplify (BinOp (Number (BitVec _ 0)) BinAnd _) = Number 0 -simplify (BinOp _ BinAnd (Number (BitVec _ 0))) = Number 0 -simplify (BinOp e BinPlus (Number (BitVec _ 0))) = e -simplify (BinOp (Number (BitVec _ 0)) BinPlus e) = e +simplify (BinOp (Number (BitVec _ 1)) BinAnd e) = e +simplify (BinOp e BinAnd (Number (BitVec _ 1))) = e +simplify (BinOp (Number (BitVec _ 0)) BinAnd _) = Number 0 +simplify (BinOp _ BinAnd (Number (BitVec _ 0))) = Number 0 +simplify (BinOp e BinPlus (Number (BitVec _ 0))) = e +simplify (BinOp (Number (BitVec _ 0)) BinPlus e) = e simplify (BinOp e BinMinus (Number (BitVec _ 0))) = e simplify (BinOp (Number (BitVec _ 0)) BinMinus e) = e simplify (BinOp e BinTimes (Number (BitVec _ 1))) = e simplify (BinOp (Number (BitVec _ 1)) BinTimes e) = e simplify (BinOp _ BinTimes (Number (BitVec _ 0))) = Number 0 simplify (BinOp (Number (BitVec _ 0)) BinTimes _) = Number 0 -simplify (BinOp e BinOr (Number (BitVec _ 0))) = e -simplify (BinOp (Number (BitVec _ 0)) BinOr e) = e -simplify (BinOp e BinLSL (Number (BitVec _ 0))) = e -simplify (BinOp (Number (BitVec _ 0)) BinLSL e) = e -simplify (BinOp e BinLSR (Number (BitVec _ 0))) = e -simplify (BinOp (Number (BitVec _ 0)) BinLSR e) = e -simplify (BinOp e BinASL (Number (BitVec _ 0))) = e -simplify (BinOp (Number (BitVec _ 0)) BinASL e) = e -simplify (BinOp e BinASR (Number (BitVec _ 0))) = e -simplify (BinOp (Number (BitVec _ 0)) BinASR e) = e -simplify (UnOp UnPlus e) = e -simplify e = e +simplify (BinOp e BinOr (Number (BitVec _ 0))) = e +simplify (BinOp (Number (BitVec _ 0)) BinOr e) = e +simplify (BinOp e BinLSL (Number (BitVec _ 0))) = e +simplify (BinOp (Number (BitVec _ 0)) BinLSL e) = e +simplify (BinOp e BinLSR (Number (BitVec _ 0))) = e +simplify (BinOp (Number (BitVec _ 0)) BinLSR e) = e +simplify (BinOp e BinASL (Number (BitVec _ 0))) = e +simplify (BinOp (Number (BitVec _ 0)) BinASL e) = e +simplify (BinOp e BinASR (Number (BitVec _ 0))) = e +simplify (BinOp (Number (BitVec _ 0)) BinASR e) = e +simplify (UnOp UnPlus e) = e +simplify e = e -- | Remove all 'Identifier' that do not appeare in the input list from an -- 'Expr'. The identifier will be replaced by @1'b0@, which can then later be diff --git a/src/VeriFuzz/Verilog/Parser.hs b/src/VeriFuzz/Verilog/Parser.hs index 68d0ef3..0820e48 100644 --- a/src/VeriFuzz/Verilog/Parser.hs +++ b/src/VeriFuzz/Verilog/Parser.hs @@ -26,17 +26,20 @@ module VeriFuzz.Verilog.Parser where import Control.Lens -import Control.Monad (void) -import Data.Bifunctor (bimap) +import Control.Monad ( void ) +import Data.Bifunctor ( bimap ) import Data.Bits -import Data.Functor (($>)) -import Data.Functor.Identity (Identity) -import Data.List (isInfixOf, isPrefixOf, null) -import Data.List.NonEmpty (NonEmpty (..)) -import Data.Text (Text) -import qualified Data.Text as T -import qualified Data.Text.IO as T -import Text.Parsec hiding (satisfy) +import Data.Functor ( ($>) ) +import Data.Functor.Identity ( Identity ) +import Data.List ( isInfixOf + , isPrefixOf + , null + ) +import Data.List.NonEmpty ( NonEmpty(..) ) +import Data.Text ( Text ) +import qualified Data.Text as T +import qualified Data.Text.IO as T +import Text.Parsec hiding ( satisfy ) import Text.Parsec.Expr import VeriFuzz.Internal import VeriFuzz.Verilog.AST diff --git a/src/VeriFuzz/Verilog/Quote.hs b/src/VeriFuzz/Verilog/Quote.hs index 362cf06..f0b7c96 100644 --- a/src/VeriFuzz/Verilog/Quote.hs +++ b/src/VeriFuzz/Verilog/Quote.hs @@ -18,8 +18,8 @@ module VeriFuzz.Verilog.Quote where import Data.Data -import qualified Data.Text as T -import qualified Language.Haskell.TH as TH +import qualified Data.Text as T +import qualified Language.Haskell.TH as TH import Language.Haskell.TH.Quote import Language.Haskell.TH.Syntax import VeriFuzz.Verilog.Parser |