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Diffstat (limited to 'src/VeriFuzz/Yosys.hs')
| -rw-r--r-- | src/VeriFuzz/Yosys.hs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/VeriFuzz/Yosys.hs b/src/VeriFuzz/Yosys.hs index b6da8c2..ef2bc11 100644 --- a/src/VeriFuzz/Yosys.hs +++ b/src/VeriFuzz/Yosys.hs @@ -37,7 +37,7 @@ defaultYosys = Yosys "yosys" writeSimFile :: Yosys -- ^ Simulator instance - -> VerilogSrc -- ^ Current Verilog source + -> Verilog -- ^ Current Verilog source -> FilePath -- ^ Output sim file -> Sh () writeSimFile _ src file = do |