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-rw-r--r--src/VeriFuzz/Verilog/Gen.hs2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/VeriFuzz/Verilog/Gen.hs b/src/VeriFuzz/Verilog/Gen.hs
index 3bfe4b9..2331068 100644
--- a/src/VeriFuzz/Verilog/Gen.hs
+++ b/src/VeriFuzz/Verilog/Gen.hs
@@ -362,7 +362,7 @@ instantiate :: ModDecl -> StateGen ModItem
instantiate (ModDecl i outP inP _ _) = do
context <- get
outs <- replicateM (length outP) (nextPort Wire)
- ins <- take (length inP - 1) <$> Hog.shuffle (context ^. variables)
+ ins <- take (length inP) <$> Hog.shuffle (context ^. variables)
sequence_ $ uncurry resizePort <$> zip (outs <> ins) (outP <> inP)
ident <- makeIdentifier "modinst"
Hog.choice