diff options
Diffstat (limited to 'src/VeriFuzz')
| -rw-r--r-- | src/VeriFuzz/Sim.hs | 10 | ||||
| -rw-r--r-- | src/VeriFuzz/Verilog/Mutate.hs | 2 |
2 files changed, 8 insertions, 4 deletions
diff --git a/src/VeriFuzz/Sim.hs b/src/VeriFuzz/Sim.hs index 794d8e9..8556983 100644 --- a/src/VeriFuzz/Sim.hs +++ b/src/VeriFuzz/Sim.hs @@ -21,12 +21,15 @@ module VeriFuzz.Sim -- ** Icarus , Icarus(..) , defaultIcarus - -- ** XST - , XST(..) - , defaultXST -- ** Yosys , Yosys(..) , defaultYosys + -- ** Vivado + , Vivado(..) + , defaultVivado + -- ** XST + , XST(..) + , defaultXST -- * Reducer , reduce -- * Equivalence @@ -43,5 +46,6 @@ import VeriFuzz.Sim.Env import VeriFuzz.Sim.Icarus import VeriFuzz.Sim.Internal import VeriFuzz.Sim.Reduce +import VeriFuzz.Sim.Vivado import VeriFuzz.Sim.XST import VeriFuzz.Sim.Yosys diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs index c72463f..69b6d57 100644 --- a/src/VeriFuzz/Verilog/Mutate.hs +++ b/src/VeriFuzz/Verilog/Mutate.hs @@ -105,7 +105,7 @@ allVars m = <> (m ^.. modInPorts . traverse . portName) -- $setup --- >>> import VeriFuzz.CodeGen +-- >>> import VeriFuzz.Verilog.CodeGen -- >>> let m = (ModDecl (Identifier "m") [Port Wire False 5 (Identifier "y")] [Port Wire False 5 "x"] []) -- >>> let main = (ModDecl "main" [] [] []) |