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-rw-r--r--src/Verismith.hs6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/Verismith.hs b/src/Verismith.hs
index e7d3ce6..85deca3 100644
--- a/src/Verismith.hs
+++ b/src/Verismith.hs
@@ -30,7 +30,7 @@ module Verismith
, module Verismith.Verilog
, module Verismith.Config
, module Verismith.Circuit
- , module Verismith.Sim
+ , module Verismith.Tool
, module Verismith.Fuzz
, module Verismith.Report
)
@@ -65,8 +65,8 @@ import Verismith.Generate
import Verismith.Reduce
import Verismith.Report
import Verismith.Result
-import Verismith.Sim
-import Verismith.Sim.Internal
+import Verismith.Tool
+import Verismith.Tool.Internal
import Verismith.Verilog
import Verismith.Verilog.Parser (parseSourceInfoFile)