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Diffstat (limited to 'src/Verismith/Generate.hs')
| -rw-r--r-- | src/Verismith/Generate.hs | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/Verismith/Generate.hs b/src/Verismith/Generate.hs index a896c3e..25b9306 100644 --- a/src/Verismith/Generate.hs +++ b/src/Verismith/Generate.hs @@ -445,6 +445,7 @@ instantiate (ModDecl i outP inP _ _) = do context <- lget outs <- replicateM (length outP) (nextPort Wire) ins <- take (length inpFixed) <$> Hog.shuffle (context ^. variables) + insLit <- replicateM (length inpFixed - length ins) (Number <$> genBitVec) mapM_ (uncurry process) . zip (ins ^.. traverse . portName) $ inpFixed ^.. traverse . portSize ident <- makeIdentifier "modinst" vs <- view variables <$> lget |