diff options
Diffstat (limited to 'src/Verismith/Tool')
-rw-r--r-- | src/Verismith/Tool/QuartusLight.hs | 78 | ||||
-rw-r--r-- | src/Verismith/Tool/Template.hs | 26 |
2 files changed, 101 insertions, 3 deletions
diff --git a/src/Verismith/Tool/QuartusLight.hs b/src/Verismith/Tool/QuartusLight.hs new file mode 100644 index 0000000..86c9a3a --- /dev/null +++ b/src/Verismith/Tool/QuartusLight.hs @@ -0,0 +1,78 @@ +{-| +Module : Verismith.Tool.QuartusLight +Description : QuartusLight synthesiser implementation. +Copyright : (c) 2019, Yann Herklotz Grave +License : GPL-3 +Maintainer : yann [at] yannherklotz [dot] com +Stability : experimental +Portability : POSIX + +QuartusLight synthesiser implementation. +-} + +module Verismith.Tool.QuartusLight + ( QuartusLight(..) + , defaultQuartusLight + ) +where + +import Control.DeepSeq (NFData, rnf, rwhnf) +import Data.Text (Text, unpack) +import Prelude hiding (FilePath) +import Shelly +import Shelly.Lifted (liftSh) +import Verismith.Tool.Internal +import Verismith.Tool.Template +import Verismith.Verilog.AST +import Verismith.Verilog.CodeGen + +data QuartusLight = QuartusLight { quartusLightBin :: !(Maybe FilePath) + , quartusLightDesc :: {-# UNPACK #-} !Text + , quartusLightOutput :: {-# UNPACK #-} !FilePath + } + deriving (Eq) + +instance Tool QuartusLight where + toText (QuartusLight _ t _) = t + +instance Show QuartusLight where + show t = unpack $ toText t + +instance Synthesiser QuartusLight where + runSynth = runSynthQuartusLight + synthOutput = quartusLightOutput + setSynthOutput (QuartusLight a b _) = QuartusLight a b + +instance NFData QuartusLight where + rnf = rwhnf + +defaultQuartusLight :: QuartusLight +defaultQuartusLight = QuartusLight Nothing "quartus" "syn_quartus.v" + +runSynthQuartusLight :: QuartusLight -> SourceInfo -> ResultSh () +runSynthQuartusLight sim (SourceInfo top src) = do + dir <- liftSh pwd + let ex = execute_ SynthFail dir "quartus" + liftSh $ do + writefile inpf $ genSource src + noPrint $ run_ "sed" [ "-i" + , "s/^module/(* multstyle = \"logic\" *) module/;" + , toTextIgnore inpf + ] + writefile quartusSdc $ "create_clock -period 5 -name clk [get_ports clock]" + writefile quartusTcl $ quartusSynthConfig sim quartusSdc top inpf + ex (exec "quartus_sh") ["-t", toTextIgnore quartusTcl] + liftSh $ do + cp (fromText "simulation/vcs" </> fromText top <.> "vo") + $ synthOutput sim + run_ + "sed" + [ "-ri" + , "s,^// DATE.*,,; s,^tri1 (.*);,wire \\1 = 1;,; /^\\/\\/ +synopsys/ d;" + , toTextIgnore $ synthOutput sim + ] + where + inpf = "rtl.v" + exec s = maybe (fromText s) (</> fromText s) $ quartusLightBin sim + quartusTcl = fromText top <.> "tcl" + quartusSdc = fromText top <.> "sdc" diff --git a/src/Verismith/Tool/Template.hs b/src/Verismith/Tool/Template.hs index 5402702..3bd5a2d 100644 --- a/src/Verismith/Tool/Template.hs +++ b/src/Verismith/Tool/Template.hs @@ -16,6 +16,7 @@ module Verismith.Tool.Template ( yosysSynthConfigStd , yosysSatConfig , yosysSimConfig + , quartusLightSynthConfig , quartusSynthConfig , xstSynthConfig , vivadoSynthConfig @@ -77,10 +78,10 @@ yosysSimConfig = [st|read_verilog rtl.v; proc;; rename mod mod_rtl |] -quartusSynthConfig :: Synthesiser a => a -> FilePath -> Text -> FilePath -> Text -quartusSynthConfig q sdc top fp = [st|load_package flow +quartusLightSynthConfig :: Synthesiser a => a -> FilePath -> Text -> FilePath -> Text +quartusLightSynthConfig q sdc top fp = [st|load_package flow -project_new #{top} +project_new -overwrite #{top} set_global_assignment -name FAMILY "Cyclone V" set_global_assignment -name SYSTEMVERILOG_FILE #{toTextIgnore fp} @@ -98,6 +99,25 @@ execute_module -tool eda -args "--simulation --tool=vcs" project_close |] +quartusSynthConfig :: Synthesiser a => a -> FilePath -> Text -> FilePath -> Text +quartusSynthConfig q sdc top fp = [st|load_package flow + +project_new -overwrite #{top} + +set_global_assignment -name FAMILY "Cyclone 10 GX" +set_global_assignment -name SYSTEMVERILOG_FILE #{toTextIgnore fp} +set_global_assignment -name TOP_LEVEL_ENTITY #{top} +set_global_assignment -name SDC_FILE #{toTextIgnore sdc} +set_global_assignment -name INI_VARS "qatm_force_vqm=on;" +set_global_assignment -name NUM_PARALLEL_PROCESSORS 2 +set_instance_assignment -name VIRTUAL_PIN ON -to * + +execute_module -tool syn +execute_module -tool eda -args "--simulation --tool=vcs" + +project_close +|] + xstSynthConfig :: Text -> Text xstSynthConfig top = [st|run -ifn #{top}.prj -ofn #{top} -p artix7 -top #{top} |