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Diffstat (limited to 'src/Verismith/Verilog.hs')
-rw-r--r-- | src/Verismith/Verilog.hs | 187 |
1 files changed, 99 insertions, 88 deletions
diff --git a/src/Verismith/Verilog.hs b/src/Verismith/Verilog.hs index f3d9e85..4de6fda 100644 --- a/src/Verismith/Verilog.hs +++ b/src/Verismith/Verilog.hs @@ -1,106 +1,117 @@ -{-| -Module : Verismith.Verilog -Description : Verilog implementation with random generation and mutations. -Copyright : (c) 2019, Yann Herklotz Grave -License : GPL-3 -Maintainer : yann [at] yannherklotz [dot] com -Stability : experimental -Portability : POSIX - -Verilog implementation with random generation and mutations. --} - {-# LANGUAGE QuasiQuotes #-} +-- | +-- Module : Verismith.Verilog +-- Description : Verilog implementation with random generation and mutations. +-- Copyright : (c) 2019, Yann Herklotz Grave +-- License : GPL-3 +-- Maintainer : yann [at] yannherklotz [dot] com +-- Stability : experimental +-- Portability : POSIX +-- +-- Verilog implementation with random generation and mutations. module Verismith.Verilog - ( SourceInfo(..) - , Verilog(..) - , parseVerilog - , GenVerilog(..) - , genSource + ( SourceInfo (..), + Verilog (..), + parseVerilog, + GenVerilog (..), + genSource, + -- * Primitives + -- ** Identifier - , Identifier(..) + Identifier (..), + -- ** Control - , Delay(..) - , Event(..) + Delay (..), + Event (..), + -- ** Operators - , BinaryOperator(..) - , UnaryOperator(..) + BinaryOperator (..), + UnaryOperator (..), + -- ** Task - , Task(..) - , taskName - , taskExpr + Task (..), + taskName, + taskExpr, + -- ** Left hand side value - , LVal(..) - , regId - , regExprId - , regExpr - , regSizeId - , regSizeRange - , regConc + LVal (..), + regId, + regExprId, + regExpr, + regSizeId, + regSizeRange, + regConc, + -- ** Ports - , PortDir(..) - , PortType(..) - , Port(..) - , portType - , portSigned - , portSize - , portName + PortDir (..), + PortType (..), + Port (..), + portType, + portSigned, + portSize, + portName, + -- * Expression - , Expr(..) - , ConstExpr(..) - , constToExpr - , exprToConst - , constNum + Expr (..), + ConstExpr (..), + constToExpr, + exprToConst, + constNum, + -- * Assignment - , Assign(..) - , assignReg - , assignDelay - , assignExpr - , ContAssign(..) - , contAssignNetLVal - , contAssignExpr + Assign (..), + assignReg, + assignDelay, + assignExpr, + ContAssign (..), + contAssignNetLVal, + contAssignExpr, + -- * Statment - , Statement(..) - , statDelay - , statDStat - , statEvent - , statEStat - , statements - , stmntBA - , stmntNBA - , stmntTask - , stmntSysTask - , stmntCondExpr - , stmntCondTrue - , stmntCondFalse + Statement (..), + statDelay, + statDStat, + statEvent, + statEStat, + statements, + stmntBA, + stmntNBA, + stmntTask, + stmntSysTask, + stmntCondExpr, + stmntCondTrue, + stmntCondFalse, + -- * Module - , ModDecl(..) - , modId - , modOutPorts - , modInPorts - , modItems - , ModItem(..) - , modContAssign - , modInstId - , modInstName - , modInstConns - , traverseModItem - , declDir - , declPort - , ModConn(..) - , modConnName - , modExpr + ModDecl (..), + modId, + modOutPorts, + modInPorts, + modItems, + ModItem (..), + modContAssign, + modInstId, + modInstName, + modInstConns, + traverseModItem, + declDir, + declPort, + ModConn (..), + modConnName, + modExpr, + -- * Useful Lenses and Traversals - , getModule - , getSourceId + getModule, + getSourceId, + -- * Quote - , verilog - ) + verilog, + ) where -import Verismith.Verilog.AST -import Verismith.Verilog.CodeGen -import Verismith.Verilog.Parser -import Verismith.Verilog.Quote +import Verismith.Verilog.AST +import Verismith.Verilog.CodeGen +import Verismith.Verilog.Parser +import Verismith.Verilog.Quote |