diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/VeriFuzz.hs | 2 | ||||
| -rw-r--r-- | src/VeriFuzz/Icarus.hs | 5 | ||||
| -rw-r--r-- | src/VeriFuzz/Mutate.hs | 12 |
3 files changed, 9 insertions, 10 deletions
diff --git a/src/VeriFuzz.hs b/src/VeriFuzz.hs index 21acf10..d583610 100644 --- a/src/VeriFuzz.hs +++ b/src/VeriFuzz.hs @@ -87,7 +87,7 @@ runSimulation = do -- head $ (nestUpTo 30 . generateAST $ Circuit gr) ^.. getVerilogSrc . traverse . getDescription rand <- genRandom 20 rand2 <- QC.generate (randomMod 10 100) - val <- shelly $ runSim defaultIcarus (rand2) rand + val <- shelly $ runSim defaultIcarus rand2 rand T.putStrLn $ showBS val onFailure :: Text -> RunFailed -> Sh () diff --git a/src/VeriFuzz/Icarus.hs b/src/VeriFuzz/Icarus.hs index b5b2b02..c8bfccd 100644 --- a/src/VeriFuzz/Icarus.hs +++ b/src/VeriFuzz/Icarus.hs @@ -24,7 +24,7 @@ import qualified Data.ByteString.Lazy as L (ByteString) import Data.Char (digitToInt) import Data.Foldable (fold) import Data.List (transpose) -import Data.Maybe (fromMaybe, listToMaybe) +import Data.Maybe (listToMaybe) import Data.Text (Text) import qualified Data.Text as T import Numeric (readInt) @@ -66,8 +66,7 @@ convert :: Text -> ByteString convert = toStrict . (encode :: Integer -> L.ByteString) - . fromMaybe 0 - . fmap fst + . maybe 0 fst . listToMaybe . readInt 2 (`elem` ("01" :: String)) digitToInt . T.unpack diff --git a/src/VeriFuzz/Mutate.hs b/src/VeriFuzz/Mutate.hs index 56db6c4..b8b1f59 100644 --- a/src/VeriFuzz/Mutate.hs +++ b/src/VeriFuzz/Mutate.hs @@ -128,8 +128,8 @@ instantiateModSpec_ outChar m = ModInst (m ^. modId) (m ^. modId) conns where conns = zipWith ModConnNamed ids (Id <$> instIds) - ids = (filterChar outChar $ name modOutPorts) ++ (name modInPorts) - instIds = (name modOutPorts) ++ (name modInPorts) + ids = filterChar outChar (name modOutPorts) <> name modInPorts + instIds = name modOutPorts <> name modInPorts name v = m ^.. v . traverse . portName filterChar :: Text -> [Identifier] -> [Identifier] @@ -172,7 +172,7 @@ makeTopAssert = (modItems %~ (++ [assert])) . (modInPorts %~ addClk) . makeTop 2 assert = Always . EventCtrl e . Just $ SeqBlock [TaskEnable $ Task "assert" [BinOp (Id "y_1") BinEq (Id "y_2")]] e = EPosEdge "clk" - addClk = ((Port Wire 1 "clk") :) + addClk = (Port Wire 1 "clk" :) -- | Provide declarations for all the ports that are passed to it. declareMod :: [Port] -> ModDecl -> ModDecl @@ -222,10 +222,10 @@ simplify e = e -- >>> GenVerilog . removeId ["x"] $ Id "x" + Id "y" -- (x + (-1'h0)) removeId :: [Identifier] -> Expr -> Expr -removeId i expr = - transform trans expr +removeId i = + transform trans where trans (Id ident) - | all (ident /=) i = Number 1 0 + | ident `notElem` i = Number 1 0 | otherwise = Id ident trans e = e |