diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/Verismith.hs (renamed from src/VeriFuzz.hs) | 311 | ||||
| -rw-r--r-- | src/Verismith/Circuit.hs (renamed from src/VeriFuzz/Circuit.hs) | 18 | ||||
| -rw-r--r-- | src/Verismith/Circuit/Base.hs (renamed from src/VeriFuzz/Circuit/Base.hs) | 4 | ||||
| -rw-r--r-- | src/Verismith/Circuit/Gen.hs (renamed from src/VeriFuzz/Circuit/Gen.hs) | 16 | ||||
| -rw-r--r-- | src/Verismith/Circuit/Internal.hs (renamed from src/VeriFuzz/Circuit/Internal.hs) | 4 | ||||
| -rw-r--r-- | src/Verismith/Circuit/Random.hs (renamed from src/VeriFuzz/Circuit/Random.hs) | 6 | ||||
| -rw-r--r-- | src/Verismith/Config.hs (renamed from src/VeriFuzz/Config.hs) | 20 | ||||
| -rw-r--r-- | src/Verismith/Fuzz.hs (renamed from src/VeriFuzz/Fuzz.hs) | 343 | ||||
| -rw-r--r-- | src/Verismith/Generate.hs (renamed from src/VeriFuzz/Generate.hs) | 123 | ||||
| -rw-r--r-- | src/Verismith/Internal.hs (renamed from src/VeriFuzz/Internal.hs) | 4 | ||||
| -rw-r--r-- | src/Verismith/OptParser.hs | 262 | ||||
| -rw-r--r-- | src/Verismith/Reduce.hs (renamed from src/VeriFuzz/Reduce.hs) | 49 | ||||
| -rw-r--r-- | src/Verismith/Report.hs (renamed from src/VeriFuzz/Report.hs) | 22 | ||||
| -rw-r--r-- | src/Verismith/Result.hs (renamed from src/VeriFuzz/Result.hs) | 6 | ||||
| -rw-r--r-- | src/Verismith/Tool.hs (renamed from src/VeriFuzz/Sim.hs) | 18 | ||||
| -rw-r--r-- | src/Verismith/Tool/Icarus.hs (renamed from src/VeriFuzz/Sim/Icarus.hs) | 67 | ||||
| -rw-r--r-- | src/Verismith/Tool/Identity.hs (renamed from src/VeriFuzz/Sim/Identity.hs) | 20 | ||||
| -rw-r--r-- | src/Verismith/Tool/Internal.hs (renamed from src/VeriFuzz/Sim/Internal.hs) | 16 | ||||
| -rw-r--r-- | src/Verismith/Tool/Quartus.hs (renamed from src/VeriFuzz/Sim/Quartus.hs) | 18 | ||||
| -rw-r--r-- | src/Verismith/Tool/Template.hs (renamed from src/VeriFuzz/Sim/Template.hs) | 42 | ||||
| -rw-r--r-- | src/Verismith/Tool/Vivado.hs (renamed from src/VeriFuzz/Sim/Vivado.hs) | 20 | ||||
| -rw-r--r-- | src/Verismith/Tool/XST.hs (renamed from src/VeriFuzz/Sim/XST.hs) | 22 | ||||
| -rw-r--r-- | src/Verismith/Tool/Yosys.hs (renamed from src/VeriFuzz/Sim/Yosys.hs) | 34 | ||||
| -rw-r--r-- | src/Verismith/Verilog.hs (renamed from src/VeriFuzz/Verilog.hs) | 12 | ||||
| -rw-r--r-- | src/Verismith/Verilog/AST.hs (renamed from src/VeriFuzz/Verilog/AST.hs) | 6 | ||||
| -rw-r--r-- | src/Verismith/Verilog/BitVec.hs (renamed from src/VeriFuzz/Verilog/BitVec.hs) | 4 | ||||
| -rw-r--r-- | src/Verismith/Verilog/CodeGen.hs (renamed from src/VeriFuzz/Verilog/CodeGen.hs) | 14 | ||||
| -rw-r--r-- | src/Verismith/Verilog/Eval.hs (renamed from src/VeriFuzz/Verilog/Eval.hs) | 14 | ||||
| -rw-r--r-- | src/Verismith/Verilog/Internal.hs (renamed from src/VeriFuzz/Verilog/Internal.hs) | 8 | ||||
| -rw-r--r-- | src/Verismith/Verilog/Lex.x (renamed from src/VeriFuzz/Verilog/Lex.x) | 4 | ||||
| -rw-r--r-- | src/Verismith/Verilog/Mutate.hs (renamed from src/VeriFuzz/Verilog/Mutate.hs) | 28 | ||||
| -rw-r--r-- | src/Verismith/Verilog/Parser.hs (renamed from src/VeriFuzz/Verilog/Parser.hs) | 38 | ||||
| -rw-r--r-- | src/Verismith/Verilog/Preprocess.hs (renamed from src/VeriFuzz/Verilog/Preprocess.hs) | 4 | ||||
| -rw-r--r-- | src/Verismith/Verilog/Quote.hs (renamed from src/VeriFuzz/Verilog/Quote.hs) | 6 | ||||
| -rw-r--r-- | src/Verismith/Verilog/Token.hs (renamed from src/VeriFuzz/Verilog/Token.hs) | 4 |
35 files changed, 841 insertions, 746 deletions
diff --git a/src/VeriFuzz.hs b/src/Verismith.hs index 4f52108..41d845d 100644 --- a/src/VeriFuzz.hs +++ b/src/Verismith.hs @@ -1,6 +1,6 @@ {-| -Module : VeriFuzz -Description : VeriFuzz +Module : Verismith +Description : Verismith Copyright : (c) 2018-2019, Yann Herklotz License : BSD-3 Maintainer : yann [at] yannherklotz [dot] com @@ -10,7 +10,7 @@ Portability : POSIX {-# OPTIONS_GHC -Wno-unused-top-binds #-} -module VeriFuzz +module Verismith ( defaultMain -- * Types , Opts(..) @@ -27,12 +27,12 @@ module VeriFuzz , proceduralSrcIO , randomMod -- * Extra modules - , module VeriFuzz.Verilog - , module VeriFuzz.Config - , module VeriFuzz.Circuit - , module VeriFuzz.Sim - , module VeriFuzz.Fuzz - , module VeriFuzz.Report + , module Verismith.Verilog + , module Verismith.Config + , module Verismith.Circuit + , module Verismith.Tool + , module Verismith.Fuzz + , module Verismith.Report ) where @@ -54,52 +54,26 @@ import Hedgehog (Gen) import qualified Hedgehog.Gen as Hog import Hedgehog.Internal.Seed (Seed) import Options.Applicative +import Paths_verismith (getDataDir) import Prelude hiding (FilePath) import Shelly hiding (command) import Shelly.Lifted (liftSh) import System.Random (randomIO) -import VeriFuzz.Circuit -import VeriFuzz.Config -import VeriFuzz.Fuzz -import VeriFuzz.Generate -import VeriFuzz.Reduce -import VeriFuzz.Report -import VeriFuzz.Result -import VeriFuzz.Sim -import VeriFuzz.Sim.Internal -import VeriFuzz.Verilog -import VeriFuzz.Verilog.Parser (parseSourceInfoFile) - -data OptTool = TYosys - | TXST - | TIcarus - -instance Show OptTool where - show TYosys = "yosys" - show TXST = "xst" - show TIcarus = "icarus" - -data Opts = Fuzz { fuzzOutput :: {-# UNPACK #-} !Text - , configFile :: !(Maybe FilePath) - , forced :: !Bool - , keepAll :: !Bool - , num :: {-# UNPACK #-} !Int - } - | Generate { mFileName :: !(Maybe FilePath) - , configFile :: !(Maybe FilePath) - } - | Parse { fileName :: {-# UNPACK #-} !FilePath - } - | Reduce { fileName :: {-# UNPACK #-} !FilePath - , top :: {-# UNPACK #-} !Text - , reduceScript :: !(Maybe FilePath) - , synthesiserDesc :: ![SynthDescription] - , rerun :: Bool - } - | ConfigOpt { writeConfig :: !(Maybe FilePath) - , configFile :: !(Maybe FilePath) - , doRandomise :: !Bool - } +import Verismith.Circuit +import Verismith.Config +import Verismith.Fuzz +import Verismith.Generate +import Verismith.OptParser +import Verismith.Reduce +import Verismith.Report +import Verismith.Result +import Verismith.Tool +import Verismith.Tool.Internal +import Verismith.Verilog +import Verismith.Verilog.Parser (parseSourceInfoFile) + +toFP :: String -> FilePath +toFP = fromText . T.pack myForkIO :: IO () -> IO (MVar ()) myForkIO io = do @@ -107,217 +81,6 @@ myForkIO io = do _ <- forkFinally io (\_ -> putMVar mvar ()) return mvar -textOption :: Mod OptionFields String -> Parser Text -textOption = fmap T.pack . strOption - -optReader :: (String -> Maybe a) -> ReadM a -optReader f = eitherReader $ \arg -> case f arg of - Just a -> Right a - Nothing -> Left $ "Cannot parse option: " <> arg - -parseSynth :: String -> Maybe OptTool -parseSynth val | val == "yosys" = Just TYosys - | val == "xst" = Just TXST - | otherwise = Nothing - -parseSynthDesc :: String -> Maybe SynthDescription -parseSynthDesc val - | val == "yosys" = Just $ SynthDescription "yosys" Nothing Nothing Nothing - | val == "vivado" = Just $ SynthDescription "vivado" Nothing Nothing Nothing - | val == "xst" = Just $ SynthDescription "xst" Nothing Nothing Nothing - | val == "quartus" = Just - $ SynthDescription "quartus" Nothing Nothing Nothing - | val == "identity" = Just - $ SynthDescription "identity" Nothing Nothing Nothing - | otherwise = Nothing - -parseSim :: String -> Maybe OptTool -parseSim val | val == "icarus" = Just TIcarus - | otherwise = Nothing - -fuzzOpts :: Parser Opts -fuzzOpts = - Fuzz - <$> textOption - ( long "output" - <> short 'o' - <> metavar "DIR" - <> help "Output directory that the fuzz run takes place in." - <> showDefault - <> value "output" - ) - <*> ( optional - . strOption - $ long "config" - <> short 'c' - <> metavar "FILE" - <> help "Config file for the current fuzz run." - ) - <*> (switch $ long "force" <> short 'f' <> help - "Overwrite the specified directory." - ) - <*> (switch $ long "keep" <> short 'k' <> help - "Keep all the directories." - ) - <*> ( option auto - $ long "num" - <> short 'n' - <> help "The number of fuzz runs that should be performed." - <> showDefault - <> value 1 - <> metavar "INT" - ) - -genOpts :: Parser Opts -genOpts = - Generate - <$> ( optional - . strOption - $ long "output" - <> short 'o' - <> metavar "FILE" - <> help "Output to a verilog file instead." - ) - <*> ( optional - . strOption - $ long "config" - <> short 'c' - <> metavar "FILE" - <> help "Config file for the generation run." - ) - -parseOpts :: Parser Opts -parseOpts = Parse . fromText . T.pack <$> strArgument - (metavar "FILE" <> help "Verilog input file.") - -reduceOpts :: Parser Opts -reduceOpts = - Reduce - . fromText - . T.pack - <$> strArgument (metavar "FILE" <> help "Verilog input file.") - <*> textOption - ( short 't' - <> long "top" - <> metavar "TOP" - <> help "Name of top level module." - <> showDefault - <> value "top" - ) - <*> ( optional - . strOption - $ long "script" - <> metavar "SCRIPT" - <> help - "Script that determines if the current file is interesting, which is determined by the script returning 0." - ) - <*> ( many - . option (optReader parseSynthDesc) - $ short 's' - <> long "synth" - <> metavar "SYNTH" - <> help "Specify synthesiser to use." - ) - <*> ( switch - $ short 'r' - <> long "rerun" - <> help - "Only rerun the current synthesis file with all the synthesisers." - ) - -configOpts :: Parser Opts -configOpts = - ConfigOpt - <$> ( optional - . strOption - $ long "output" - <> short 'o' - <> metavar "FILE" - <> help "Output to a TOML Config file." - ) - <*> ( optional - . strOption - $ long "config" - <> short 'c' - <> metavar "FILE" - <> help "Config file for the current fuzz run." - ) - <*> ( switch - $ long "randomise" - <> short 'r' - <> help - "Randomise the given default config, or the default config by randomly switchin on and off options." - ) - -argparse :: Parser Opts -argparse = - hsubparser - ( command - "fuzz" - (info - fuzzOpts - (progDesc - "Run fuzzing on the specified simulators and synthesisers." - ) - ) - <> metavar "fuzz" - ) - <|> hsubparser - ( command - "generate" - (info - genOpts - (progDesc "Generate a random Verilog program.") - ) - <> metavar "generate" - ) - <|> hsubparser - ( command - "parse" - (info - parseOpts - (progDesc - "Parse a verilog file and output a pretty printed version." - ) - ) - <> metavar "parse" - ) - <|> hsubparser - ( command - "reduce" - (info - reduceOpts - (progDesc - "Reduce a Verilog file by rerunning the fuzzer on the file." - ) - ) - <> metavar "reduce" - ) - <|> hsubparser - ( command - "config" - (info - configOpts - (progDesc - "Print the current configuration of the fuzzer." - ) - ) - <> metavar "config" - ) - -version :: Parser (a -> a) -version = infoOption versionInfo $ mconcat - [long "version", short 'v', help "Show version information.", hidden] - -opts :: ParserInfo Opts -opts = info - (argparse <**> helper <**> version) - ( fullDesc - <> progDesc "Fuzz different simulators and synthesisers." - <> header - "VeriFuzz - A hardware simulator and synthesiser Verilog fuzzer." - ) - getConfig :: Maybe FilePath -> IO Config getConfig s = maybe (return defaultConfig) parseConfigFile $ T.unpack . toTextIgnore <$> s @@ -363,12 +126,14 @@ randomise config@(Config a _ c d e) = do ce = config ^. configProbability . probExpr handleOpts :: Opts -> IO () -handleOpts (Fuzz o configF _ _ n) = do +handleOpts (Fuzz o configF f k n nosim noequiv noreduction) = do config <- getConfig configF + datadir <- getDataDir _ <- runFuzz - config + (FuzzOpts (Just $ fromText o) + f k n nosim noequiv noreduction config (toFP datadir)) defaultYosys - (fuzzMultiple n (Just $ fromText o) (proceduralSrc "top" config)) + (fuzzMultiple (proceduralSrc "top" config)) return () handleOpts (Generate f c) = do config <- getConfig c @@ -385,13 +150,14 @@ handleOpts (Parse f) = do where file = T.unpack . toTextIgnore $ f handleOpts (Reduce f t _ ls' False) = do src <- parseSourceInfoFile t (toTextIgnore f) + datadir <- getDataDir case descriptionToSynth <$> ls' of a : b : _ -> do putStrLn "Reduce with equivalence check" shelly $ do make dir pop dir $ do - src' <- reduceSynth a b src + src' <- reduceSynth (toFP datadir) a b src writefile (fromText ".." </> dir <.> "v") $ genSource src' a : _ -> do putStrLn "Reduce with synthesis failure" @@ -406,6 +172,7 @@ handleOpts (Reduce f t _ ls' False) = do where dir = fromText "reduce" handleOpts (Reduce f t _ ls' True) = do src <- parseSourceInfoFile t (toTextIgnore f) + datadir <- getDataDir case descriptionToSynth <$> ls' of a : b : _ -> do putStrLn "Starting equivalence check" @@ -414,7 +181,7 @@ handleOpts (Reduce f t _ ls' True) = do pop dir $ do runSynth a src runSynth b src - runEquiv a b src + runEquiv (toFP datadir) a b src case res of Pass _ -> putStrLn "Equivalence check passed" Fail EquivFail -> putStrLn "Equivalence check failed" @@ -504,10 +271,11 @@ checkEquivalence :: SourceInfo -> Text -> IO Bool checkEquivalence src dir = shellyFailDir $ do mkdir_p (fromText dir) curr <- toTextIgnore <$> pwd - setenv "VERIFUZZ_ROOT" curr + datadir <- liftIO getDataDir + setenv "VERISMITH_ROOT" curr cd (fromText dir) catch_sh - ((runResultT $ runEquiv defaultYosys defaultVivado src) >> return True) + ((runResultT $ runEquiv (toFP datadir) defaultYosys defaultVivado src) >> return True) ((\_ -> return False) :: RunFailed -> Sh Bool) -- | Run a fuzz run and check if all of the simulators passed by checking if the @@ -524,15 +292,16 @@ runEquivalence seed gm t d k i = do (_, m) <- shelly $ sampleSeed seed gm let srcInfo = SourceInfo "top" m rand <- generateByteString 20 + datadir <- getDataDir shellyFailDir $ do mkdir_p (fromText d </> fromText n) curr <- toTextIgnore <$> pwd - setenv "VERIFUZZ_ROOT" curr + setenv "VERISMITH_ROOT" curr cd (fromText "output" </> fromText n) _ <- catch_sh ( runResultT - $ runEquiv defaultYosys defaultVivado srcInfo + $ runEquiv (toFP datadir) defaultYosys defaultVivado srcInfo >> liftSh (logger "Test OK") ) $ onFailure n diff --git a/src/VeriFuzz/Circuit.hs b/src/Verismith/Circuit.hs index 6083c8e..81eec12 100644 --- a/src/VeriFuzz/Circuit.hs +++ b/src/Verismith/Circuit.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Circuit +Module : Verismith.Circuit Description : Definition of the circuit graph. Copyright : (c) 2018-2019, Yann Herklotz License : BSD-3 @@ -10,7 +10,7 @@ Portability : POSIX Definition of the circuit graph. -} -module VeriFuzz.Circuit +module Verismith.Circuit ( -- * Circuit Gate(..) , Circuit(..) @@ -26,13 +26,13 @@ module VeriFuzz.Circuit where import Control.Lens -import Hedgehog (Gen) -import qualified Hedgehog.Gen as Hog -import VeriFuzz.Circuit.Base -import VeriFuzz.Circuit.Gen -import VeriFuzz.Circuit.Random -import VeriFuzz.Verilog.AST -import VeriFuzz.Verilog.Mutate +import Hedgehog (Gen) +import qualified Hedgehog.Gen as Hog +import Verismith.Circuit.Base +import Verismith.Circuit.Gen +import Verismith.Circuit.Random +import Verismith.Verilog.AST +import Verismith.Verilog.Mutate fromGraph :: Gen ModDecl fromGraph = do diff --git a/src/VeriFuzz/Circuit/Base.hs b/src/Verismith/Circuit/Base.hs index 0bcdf39..9a5ab34 100644 --- a/src/VeriFuzz/Circuit/Base.hs +++ b/src/Verismith/Circuit/Base.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Circuit.Base +Module : Verismith.Circuit.Base Description : Base types for the circuit module. Copyright : (c) 2019, Yann Herklotz Grave License : GPL-3 @@ -10,7 +10,7 @@ Portability : POSIX Base types for the circuit module. -} -module VeriFuzz.Circuit.Base +module Verismith.Circuit.Base ( Gate(..) , Circuit(..) , CNode(..) diff --git a/src/VeriFuzz/Circuit/Gen.hs b/src/Verismith/Circuit/Gen.hs index eb7cb97..c5cb697 100644 --- a/src/VeriFuzz/Circuit/Gen.hs +++ b/src/Verismith/Circuit/Gen.hs @@ -10,18 +10,18 @@ Portability : POSIX Generate verilog from circuit. -} -module VeriFuzz.Circuit.Gen +module Verismith.Circuit.Gen ( generateAST ) where -import Data.Graph.Inductive (LNode, Node) -import qualified Data.Graph.Inductive as G -import Data.Maybe (catMaybes) -import VeriFuzz.Circuit.Base -import VeriFuzz.Circuit.Internal -import VeriFuzz.Verilog.AST -import VeriFuzz.Verilog.Mutate +import Data.Graph.Inductive (LNode, Node) +import qualified Data.Graph.Inductive as G +import Data.Maybe (catMaybes) +import Verismith.Circuit.Base +import Verismith.Circuit.Internal +import Verismith.Verilog.AST +import Verismith.Verilog.Mutate -- | Converts a 'CNode' to an 'Identifier'. frNode :: Node -> Identifier diff --git a/src/VeriFuzz/Circuit/Internal.hs b/src/Verismith/Circuit/Internal.hs index 17e1586..4de2252 100644 --- a/src/VeriFuzz/Circuit/Internal.hs +++ b/src/Verismith/Circuit/Internal.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Circuit.Internal +Module : Verismith.Circuit.Internal Description : Internal helpers for generation. Copyright : (c) 2018-2019, Yann Herklotz License : BSD-3 @@ -10,7 +10,7 @@ Portability : POSIX Internal helpers for generation. -} -module VeriFuzz.Circuit.Internal +module Verismith.Circuit.Internal ( fromNode , filterGr , only diff --git a/src/VeriFuzz/Circuit/Random.hs b/src/Verismith/Circuit/Random.hs index fdb5253..0eabf56 100644 --- a/src/VeriFuzz/Circuit/Random.hs +++ b/src/Verismith/Circuit/Random.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Circuit.Random +Module : Verismith.Circuit.Random Description : Random generation for DAG Copyright : (c) 2018-2019, Yann Herklotz License : BSD-3 @@ -10,7 +10,7 @@ Portability : POSIX Define the random generation for the directed acyclic graph. -} -module VeriFuzz.Circuit.Random +module Verismith.Circuit.Random ( rDups , rDupsCirc , randomDAG @@ -25,7 +25,7 @@ import Data.List (nub) import Hedgehog (Gen) import qualified Hedgehog.Gen as Hog import qualified Hedgehog.Range as Hog -import VeriFuzz.Circuit.Base +import Verismith.Circuit.Base dupFolder :: (Eq a, Eq b) => Context a b -> [Context a b] -> [Context a b] dupFolder cont ns = unique cont : ns diff --git a/src/VeriFuzz/Config.hs b/src/Verismith/Config.hs index c986888..bf79683 100644 --- a/src/VeriFuzz/Config.hs +++ b/src/Verismith/Config.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Config +Module : Verismith.Config Description : Configuration file format and parser. Copyright : (c) 2019, Yann Herklotz License : GPL-3 @@ -12,7 +12,7 @@ TOML Configuration file format and parser. {-# LANGUAGE TemplateHaskell #-} -module VeriFuzz.Config +module Verismith.Config ( -- * TOML Configuration -- $conf Config(..) @@ -88,18 +88,18 @@ import qualified Data.Text.IO as T import Data.Version (showVersion) import Development.GitRev import Hedgehog.Internal.Seed (Seed) -import Paths_verifuzz (version) +import Paths_verismith (version) import Shelly (toTextIgnore) import Toml (TomlCodec, (.=)) import qualified Toml -import VeriFuzz.Sim.Quartus -import VeriFuzz.Sim.Vivado -import VeriFuzz.Sim.XST -import VeriFuzz.Sim.Yosys +import Verismith.Tool.Quartus +import Verismith.Tool.Vivado +import Verismith.Tool.XST +import Verismith.Tool.Yosys -- $conf -- --- VeriFuzz supports a TOML configuration file that can be passed using the @-c@ +-- Verismith supports a TOML configuration file that can be passed using the @-c@ -- flag or using the 'parseConfig' and 'encodeConfig' functions. The -- configuration can then be manipulated using the lenses that are also provided -- in this module. @@ -111,7 +111,7 @@ import VeriFuzz.Sim.Yosys -- exact generation. A default value is associated with each key in the -- configuration file, which means that only the options that need overriding -- can be added to the configuration. The defaults can be observed in --- 'defaultConfig' or when running @verifuzz config@. +-- 'defaultConfig' or when running @verismith config@. -- -- == Configuration Sections -- @@ -502,7 +502,7 @@ encodeConfigFile f = T.writeFile f . encodeConfig versionInfo :: String versionInfo = - "VeriFuzz " + "Verismith " <> showVersion version <> " (" <> $(gitCommitDate) diff --git a/src/VeriFuzz/Fuzz.hs b/src/Verismith/Fuzz.hs index df0ee2d..d14e74b 100644 --- a/src/VeriFuzz/Fuzz.hs +++ b/src/Verismith/Fuzz.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Fuzz +Module : Verismith.Fuzz Description : Environment to run the simulator and synthesisers in a matrix. Copyright : (c) 2019, Yann Herklotz License : GPL-3 @@ -14,8 +14,9 @@ Environment to run the simulator and synthesisers in a matrix. {-# LANGUAGE FlexibleContexts #-} {-# LANGUAGE TemplateHaskell #-} -module VeriFuzz.Fuzz - ( Fuzz +module Verismith.Fuzz + ( Fuzz (..) + , FuzzOpts (..) , fuzz , fuzzInDir , fuzzMultiple @@ -27,50 +28,77 @@ module VeriFuzz.Fuzz ) where -import Control.DeepSeq (force) -import Control.Exception.Lifted (finally) -import Control.Lens hiding ((<.>)) -import Control.Monad (forM, replicateM) +import Control.DeepSeq (force) +import Control.Exception.Lifted (finally) +import Control.Lens hiding ((<.>)) +import Control.Monad (forM, replicateM) import Control.Monad.IO.Class -import Control.Monad.Trans.Class (lift) -import Control.Monad.Trans.Control (MonadBaseControl) -import Control.Monad.Trans.Maybe (runMaybeT) -import Control.Monad.Trans.Reader hiding (local) -import Control.Monad.Trans.State.Strict -import qualified Crypto.Random.DRBG as C -import Data.ByteString (ByteString) -import Data.List (nubBy, sort) -import Data.Maybe (isNothing) -import Data.Text (Text) -import qualified Data.Text as T +import Control.Monad.Reader +import Control.Monad.State.Strict +import Control.Monad.Trans.Control (MonadBaseControl) +import qualified Crypto.Random.DRBG as C +import Data.ByteString (ByteString) +import Data.List (nubBy, sort) +import Data.Maybe (fromMaybe, isNothing) +import Data.Text (Text) +import qualified Data.Text as T import Data.Time -import Data.Tuple (swap) -import Hedgehog (Gen) -import qualified Hedgehog.Internal.Gen as Hog -import Hedgehog.Internal.Seed (Seed) -import qualified Hedgehog.Internal.Seed as Hog -import qualified Hedgehog.Internal.Tree as Hog -import Prelude hiding (FilePath) -import Shelly hiding (get) -import Shelly.Lifted (MonadSh, liftSh) -import System.FilePath.Posix (takeBaseName) -import VeriFuzz.Config -import VeriFuzz.Internal -import VeriFuzz.Reduce -import VeriFuzz.Report -import VeriFuzz.Result -import VeriFuzz.Sim.Icarus -import VeriFuzz.Sim.Internal -import VeriFuzz.Sim.Yosys -import VeriFuzz.Verilog.AST -import VeriFuzz.Verilog.CodeGen - -data FuzzEnv = FuzzEnv { getSynthesisers :: ![SynthTool] - , getSimulators :: ![SimTool] - , yosysInstance :: {-# UNPACK #-} !Yosys +import Data.Tuple (swap) +import Hedgehog (Gen) +import qualified Hedgehog.Internal.Gen as Hog +import Hedgehog.Internal.Seed (Seed) +import qualified Hedgehog.Internal.Seed as Hog +import qualified Hedgehog.Internal.Tree as Hog +import Prelude hiding (FilePath) +import Shelly hiding (get) +import Shelly.Lifted (MonadSh, liftSh) +import System.FilePath.Posix (takeBaseName) +import Verismith.Config +import Verismith.Internal +import Verismith.Reduce +import Verismith.Report +import Verismith.Result +import Verismith.Tool.Icarus +import Verismith.Tool.Internal +import Verismith.Tool.Yosys +import Verismith.Verilog.AST +import Verismith.Verilog.CodeGen + +data FuzzOpts = FuzzOpts { _fuzzOptsOutput :: !(Maybe FilePath) + , _fuzzOptsForced :: !Bool + , _fuzzOptsKeepAll :: !Bool + , _fuzzOptsIterations :: {-# UNPACK #-} !Int + , _fuzzOptsNoSim :: !Bool + , _fuzzOptsNoEquiv :: !Bool + , _fuzzOptsNoReduction :: !Bool + , _fuzzOptsConfig :: {-# UNPACK #-} !Config + , _fuzzDataDir :: {-# UNPACK #-} !FilePath + } + deriving (Show, Eq) + +$(makeLenses ''FuzzOpts) + +defaultFuzzOpts :: FuzzOpts +defaultFuzzOpts = FuzzOpts { _fuzzOptsOutput = Nothing + , _fuzzOptsForced = False + , _fuzzOptsKeepAll = False + , _fuzzOptsIterations = 1 + , _fuzzOptsNoSim = False + , _fuzzOptsNoEquiv = False + , _fuzzOptsNoReduction = False + , _fuzzOptsConfig = defaultConfig + , _fuzzDataDir = fromText "." + } + +data FuzzEnv = FuzzEnv { _getSynthesisers :: ![SynthTool] + , _getSimulators :: ![SimTool] + , _yosysInstance :: {-# UNPACK #-} !Yosys + , _fuzzEnvOpts :: {-# UNPACK #-} !FuzzOpts } deriving (Eq, Show) +$(makeLenses ''FuzzEnv) + data FuzzState = FuzzState { _fuzzSynthResults :: ![SynthResult] , _fuzzSimResults :: ![SimResult] , _fuzzSynthStatus :: ![SynthStatus] @@ -87,23 +115,74 @@ type Fuzz m = StateT FuzzState (ReaderT FuzzEnv m) type MonadFuzz m = (MonadBaseControl IO m, MonadIO m, MonadSh m) -runFuzz :: MonadIO m => Config -> Yosys -> (Config -> Fuzz Sh a) -> m a -runFuzz conf yos m = shelly $ runFuzz' conf yos m - -runFuzz' :: Monad m => Config -> Yosys -> (Config -> Fuzz m b) -> m b -runFuzz' conf yos m = runReaderT - (evalStateT (m conf) (FuzzState [] [] [])) - (FuzzEnv - ( force - $ defaultIdentitySynth - : (descriptionToSynth <$> conf ^. configSynthesisers) - ) - (force $ descriptionToSim <$> conf ^. configSimulators) - yos +runFuzz :: MonadIO m => FuzzOpts -> Yosys -> Fuzz Sh a -> m a +runFuzz fo yos m = shelly $ runFuzz' fo yos m + +runFuzz' :: Monad m => FuzzOpts -> Yosys -> Fuzz m b -> m b +runFuzz' fo yos m = runReaderT + (evalStateT m (FuzzState [] [] [])) + (FuzzEnv { _getSynthesisers = ( force + $ defaultIdentitySynth + : (descriptionToSynth <$> conf ^. configSynthesisers) + ) + , _getSimulators = (force $ descriptionToSim <$> conf ^. configSimulators) + , _yosysInstance = yos + , _fuzzEnvOpts = fo + } ) + where + conf = _fuzzOptsConfig fo + +askConfig :: Monad m => Fuzz m Config +askConfig = asks (_fuzzOptsConfig . _fuzzEnvOpts) + +askOpts :: Monad m => Fuzz m FuzzOpts +askOpts = asks _fuzzEnvOpts + +genMethod conf seed gen = + case T.toLower $ conf ^. configProperty . propSampleMethod of + "hat" -> do + logT "Using the hat function" + sv hatFreqs + "mean" -> do + logT "Using the mean function" + sv meanFreqs + "median" -> do + logT "Using the median function" + sv medianFreqs + _ -> do + logT "Using first seed" + sampleSeed seed gen + where + sv a = sampleVerilog a (conf ^. configProperty . propSampleSize) seed gen + +relativeFuzzReport :: (MonadSh m) => FuzzReport -> m FuzzReport +relativeFuzzReport fr@(FuzzReport dir _ _ _ _ _ _ _) = liftSh $ do + newPath <- relPath dir + return $ (fuzzDir .~ newPath) fr + +filterSynth :: SynthResult -> Bool +filterSynth (SynthResult _ _ (Pass _) _) = True +filterSynth _ = False + +filterSim :: SimResult -> Bool +filterSim (SimResult _ _ (Pass _) _) = True +filterSim _ = False + +filterSynthStat :: SynthStatus -> Bool +filterSynthStat (SynthStatus _ (Pass _) _) = True +filterSynthStat _ = False + +passedFuzz :: FuzzReport -> Bool +passedFuzz (FuzzReport _ synth sim synthstat _ _ _ _) = + (passedSynth + passedSim + passedSynthStat) == 0 + where + passedSynth = length $ filter (not . filterSynth) synth + passedSim = length $ filter (not . filterSim) sim + passedSynthStat = length $ filter (not . filterSynthStat) synthstat synthesisers :: Monad m => Fuzz m [SynthTool] -synthesisers = lift $ asks getSynthesisers +synthesisers = lift $ asks _getSynthesisers --simulators :: (Monad m) => Fuzz () m [SimTool] --simulators = lift $ asks getSimulators @@ -148,9 +227,7 @@ failedSynthesis = fmap toSynth . filter failed . _fuzzSynthStatus <$> get toSynth (SynthStatus s _ _) = s make :: MonadSh m => FilePath -> m () -make f = liftSh $ do - mkdir_p f - cp_r "data" $ f </> fromText "data" +make f = liftSh $ mkdir_p f pop :: (MonadBaseControl IO m, MonadSh m) => FilePath -> m a -> m a pop f a = do @@ -178,6 +255,7 @@ toolRun t m = do equivalence :: (MonadBaseControl IO m, MonadSh m) => SourceInfo -> Fuzz m () equivalence src = do + datadir <- fmap _fuzzDataDir askOpts synth <- passedSynthesis -- let synthComb = -- nubBy tupEq . filter (uncurry (/=)) $ combinations synth synth @@ -186,54 +264,49 @@ equivalence src = do . filter (uncurry (/=)) $ (,) defaultIdentitySynth <$> synth - resTimes <- liftSh $ mapM (uncurry equiv) synthComb + resTimes <- liftSh $ mapM (uncurry (equiv datadir)) synthComb fuzzSynthResults .= toSynthResult synthComb resTimes liftSh $ inspect resTimes where tupEq (a, b) (a', b') = (a == a' && b == b') || (a == b' && b == a') - equiv a b = + equiv datadir a b = toolRun ("equivalence check for " <> toText a <> " and " <> toText b) . runResultT - $ do - make dir - pop dir $ do - liftSh $ do - cp - ( fromText ".." - </> fromText (toText a) - </> synthOutput a - ) - $ synthOutput a - cp - ( fromText ".." - </> fromText (toText b) - </> synthOutput b - ) - $ synthOutput b - writefile "rtl.v" $ genSource src - runEquiv a b src + $ do make dir + pop dir $ do + liftSh $ do + cp ( fromText ".." + </> fromText (toText a) + </> synthOutput a + ) $ synthOutput a + cp ( fromText ".." + </> fromText (toText b) + </> synthOutput b + ) $ synthOutput b + writefile "rtl.v" $ genSource src + runEquiv datadir a b src where dir = fromText $ "equiv_" <> toText a <> "_" <> toText b simulation :: (MonadIO m, MonadSh m) => SourceInfo -> Fuzz m () simulation src = do - synth <- passEquiv + datadir <- fmap _fuzzDataDir askOpts + synth <- passedSynthesis vals <- liftIO $ generateByteString 20 - ident <- liftSh $ equiv vals defaultIdentitySynth - resTimes <- liftSh $ mapM (equiv vals) $ conv <$> synth + ident <- liftSh $ equiv datadir vals defaultIdentitySynth + resTimes <- liftSh $ mapM (equiv datadir vals) synth liftSh . inspect $ (\(_, r) -> bimap show (T.unpack . T.take 10 . showBS) r) <$> (ident : resTimes) where - conv (SynthResult _ a _ _) = a - equiv b a = toolRun ("simulation for " <> toText a) . runResultT $ do + equiv datadir b a = toolRun ("simulation for " <> toText a) . runResultT $ do make dir pop dir $ do liftSh $ do cp (fromText ".." </> fromText (toText a) </> synthOutput a) $ synthOutput a writefile "rtl.v" $ genSource src - runSimIc defaultIcarus a src b + runSimIc datadir defaultIcarus a src b where dir = fromText $ "simulation_" <> toText a -- | Generate a specific number of random bytestrings of size 256. @@ -265,16 +338,17 @@ passEquiv = filter withIdentity . _fuzzSynthResults <$> get -- | Always reduces with respect to 'Identity'. reduction :: (MonadSh m) => SourceInfo -> Fuzz m () reduction src = do + datadir <- fmap _fuzzDataDir askOpts fails <- failEquivWithIdentity synthFails <- failedSynthesis - _ <- liftSh $ mapM red fails + _ <- liftSh $ mapM (red datadir) fails _ <- liftSh $ mapM redSynth synthFails return () where - red (SynthResult a b _ _) = do + red datadir (SynthResult a b _ _) = do make dir pop dir $ do - s <- reduceSynth a b src + s <- reduceSynth datadir a b src writefile (fromText ".." </> dir <.> "v") $ genSource s return s where dir = fromText $ "reduce_" <> toText a <> "_" <> toText b @@ -351,9 +425,12 @@ medianFreqs l = zip hat (return <$> l) hat = set_ <$> [1 .. length l] set_ n = if n == h then 1 else 0 -fuzz :: MonadFuzz m => Gen SourceInfo -> Config -> Fuzz m FuzzReport -fuzz gen conf = do - (seed', src) <- generateSample genMethod +fuzz :: MonadFuzz m => Gen SourceInfo -> Fuzz m FuzzReport +fuzz gen = do + conf <- askConfig + opts <- askOpts + let seed = conf ^. configProperty . propSeed + (seed', src) <- generateSample $ genMethod conf seed gen let size = length . lines . T.unpack $ genSource src liftSh . writefile "config.toml" @@ -363,12 +440,17 @@ fuzz gen conf = do . propSeed ?~ seed' (tsynth, _) <- titleRun "Synthesis" $ synthesis src - (tequiv, _) <- titleRun "Equivalence Check" $ equivalence src - (_ , _) <- titleRun "Simulation" $ simulation src + (tequiv, _) <- if (_fuzzOptsNoEquiv opts) + then return (0, mempty) + else titleRun "Equivalence Check" $ equivalence src + (_ , _) <- if (_fuzzOptsNoSim opts) + then return (0, mempty) + else titleRun "Simulation" $ simulation src fails <- failEquivWithIdentity synthFails <- failedSynthesis redResult <- - whenMaybe (not $ null fails && null synthFails) + whenMaybe (not (null fails && null synthFails) + && not (_fuzzOptsNoReduction opts)) . titleRun "Reduction" $ reduction src state_ <- get @@ -382,47 +464,29 @@ fuzz gen conf = do tsynth tequiv (getTime redResult) - liftSh . writefile "index.html" $ printResultReport (bname currdir) report return report - where - seed = conf ^. configProperty . propSeed - bname = T.pack . takeBaseName . T.unpack . toTextIgnore - genMethod = case T.toLower $ conf ^. configProperty . propSampleMethod of - "hat" -> do - logT "Using the hat function" - sv hatFreqs - "mean" -> do - logT "Using the mean function" - sv meanFreqs - "median" -> do - logT "Using the median function" - sv medianFreqs - _ -> do - logT "Using first seed" - sampleSeed seed gen - sv a = sampleVerilog a (conf ^. configProperty . propSampleSize) seed gen -relativeFuzzReport :: (MonadSh m) => FuzzReport -> m FuzzReport -relativeFuzzReport fr@(FuzzReport dir _ _ _ _ _ _ _) = liftSh $ do - newPath <- relPath dir - return $ (fuzzDir .~ newPath) fr - -fuzzInDir - :: MonadFuzz m => FilePath -> Gen SourceInfo -> Config -> Fuzz m FuzzReport -fuzzInDir fp src conf = do +fuzzInDir :: MonadFuzz m => Gen SourceInfo -> Fuzz m FuzzReport +fuzzInDir src = do + fuzzOpts <- askOpts + let fp = fromMaybe "fuzz" $ _fuzzOptsOutput fuzzOpts make fp - res <- pop fp $ fuzz src conf + res <- pop fp $ fuzz src + liftSh $ do + writefile (fp <.> "html") $ printResultReport (bname fp) res + when (passedFuzz res && not (_fuzzOptsKeepAll fuzzOpts)) $ rm_rf fp relativeFuzzReport res + where + bname = T.pack . takeBaseName . T.unpack . toTextIgnore fuzzMultiple :: MonadFuzz m - => Int - -> Maybe FilePath - -> Gen SourceInfo - -> Config + => Gen SourceInfo -> Fuzz m [FuzzReport] -fuzzMultiple n fp src conf = do - x <- case fp of +fuzzMultiple src = do + fuzzOpts <- askOpts + let seed = (_fuzzOptsConfig fuzzOpts) ^. configProperty . propSeed + x <- case _fuzzOptsOutput fuzzOpts of Nothing -> do ct <- liftIO getZonedTime return @@ -434,33 +498,30 @@ fuzzMultiple n fp src conf = do make x pop x $ do results <- if isNothing seed - then forM [1 .. n] fuzzDir' + then forM [1 .. (_fuzzOptsIterations fuzzOpts)] fuzzDir' else (: []) <$> fuzzDir' (1 :: Int) liftSh . writefile (fromText "index" <.> "html") $ printSummary "Fuzz Summary" results return results where - fuzzDir' n' = fuzzInDir (fromText $ "fuzz_" <> showT n') src conf - seed = conf ^. configProperty . propSeed + fuzzDir' :: (Show a, MonadFuzz m) => a -> Fuzz m FuzzReport + fuzzDir' n' = local (fuzzEnvOpts . fuzzOptsOutput .~ + (Just . fromText $ "fuzz_" <> showT n')) + $ fuzzInDir src sampleSeed :: MonadSh m => Maybe Seed -> Gen a -> m (Seed, a) sampleSeed s gen = liftSh - $ let - loop n = if n <= 0 + $ let loop n = if n <= 0 then error "Hedgehog.Gen.sample: too many discards, could not generate a sample" else do seed <- maybe Hog.random return s - case - runIdentity - . runMaybeT - . Hog.runTree - $ Hog.runGenT 30 seed gen - of - Nothing -> loop (n - 1) - Just x -> return (seed, Hog.nodeValue x) + case Hog.evalGen 30 seed gen of + Nothing -> + loop (n - 1) + Just x -> + pure (seed, Hog.treeValue x) in loop (100 :: Int) - diff --git a/src/VeriFuzz/Generate.hs b/src/Verismith/Generate.hs index d081504..8dba3fa 100644 --- a/src/VeriFuzz/Generate.hs +++ b/src/Verismith/Generate.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Generate +Module : Verismith.Generate Description : Various useful generators. Copyright : (c) 2019, Yann Herklotz License : GPL-3 @@ -10,10 +10,11 @@ Portability : POSIX Various useful generators. -} -{-# LANGUAGE TemplateHaskell #-} +{-# LANGUAGE FlexibleContexts #-} +{-# LANGUAGE TemplateHaskell #-} {-# OPTIONS_GHC -Wno-unused-imports #-} -module VeriFuzz.Generate +module Verismith.Generate ( -- * Generation methods procedural , proceduralIO @@ -21,7 +22,6 @@ module VeriFuzz.Generate , proceduralSrcIO , randomMod -- ** Generate Functions - , gen , largeNum , wireSize , range @@ -61,25 +61,25 @@ module VeriFuzz.Generate ) where -import Control.Lens hiding (Context) -import Control.Monad (replicateM) -import Control.Monad.Trans.Class (lift) -import Control.Monad.Trans.Reader hiding (local) -import Control.Monad.Trans.State.Strict -import Data.Foldable (fold) -import Data.Functor.Foldable (cata) -import Data.List (foldl', partition) -import qualified Data.Text as T -import Hedgehog (Gen) -import qualified Hedgehog.Gen as Hog -import qualified Hedgehog.Range as Hog -import VeriFuzz.Config -import VeriFuzz.Internal -import VeriFuzz.Verilog.AST -import VeriFuzz.Verilog.BitVec -import VeriFuzz.Verilog.Eval -import VeriFuzz.Verilog.Internal -import VeriFuzz.Verilog.Mutate +import Control.Lens hiding (Context) +import Control.Monad (replicateM) +import Control.Monad.Reader +import Control.Monad.State.Strict +import Data.Foldable (fold) +import Data.Functor.Foldable (cata) +import Data.List (foldl', partition) +import qualified Data.Text as T +import Hedgehog (Gen, GenT, MonadGen) +import qualified Hedgehog as Hog +import qualified Hedgehog.Gen as Hog +import qualified Hedgehog.Range as Hog +import Verismith.Config +import Verismith.Internal +import Verismith.Verilog.AST +import Verismith.Verilog.BitVec +import Verismith.Verilog.Eval +import Verismith.Verilog.Internal +import Verismith.Verilog.Mutate data PortInfo = PortInfo { _portInfoPort :: {-# UNPACK #-} !Port , _portInfoDet :: !Bool @@ -98,7 +98,7 @@ data Context = Context { _contextVariables :: ![PortInfo] $(makeLenses ''Context) -type StateGen = StateT Context (ReaderT Config Gen) +type StateGen = ReaderT Config (GenT (State Context)) fromPort :: Port -> PortInfo fromPort p = PortInfo p True @@ -112,7 +112,7 @@ _portsFromContext c = c ^.. contextVariables . traverse . portInfoPort toId :: Int -> Identifier toId = Identifier . ("w" <>) . T.pack . show -toPort :: Identifier -> Gen Port +toPort :: (MonadGen m) => Identifier -> m Port toPort ident = do i <- range return $ wire i ident @@ -132,7 +132,7 @@ legacySafeProb = ProbExpr { _probExprNum = 1 , _probExprUnsigned = 1 } -random :: [Port] -> (Expr -> ContAssign) -> Gen ModItem +random :: (MonadGen m) => [Port] -> (Expr -> ContAssign) -> m ModItem random ctx fun = do expr <- Hog.sized (exprWithContext legacySafeProb [] ctx) return . ModCA $ fun expr @@ -140,12 +140,12 @@ random ctx fun = do --randomAssigns :: [Identifier] -> [Gen ModItem] --randomAssigns ids = random ids . ContAssign <$> ids -randomOrdAssigns :: [Port] -> [Port] -> [Gen ModItem] +randomOrdAssigns :: (MonadGen m) => [Port] -> [Port] -> [m ModItem] randomOrdAssigns inp ids = snd $ foldr generate (inp, []) ids where generate cid (i, o) = (cid : i, random i (ContAssign (_portName cid)) : o) -randomMod :: Int -> Int -> Gen ModDecl +randomMod :: (MonadGen m) => Int -> Int -> m ModDecl randomMod inps total = do ident <- sequence $ toPort <$> ids x <- sequence $ randomOrdAssigns (start ident) (end ident) @@ -174,27 +174,23 @@ probability c = c ^. configProbability -- | Gets the current probabilities from the 'State'. askProbability :: StateGen Probability -askProbability = lift $ asks probability - --- | Lifts a 'Gen' into the 'StateGen' monad. -gen :: Gen a -> StateGen a -gen = lift . lift +askProbability = asks probability -- | Generates a random large number, which can also be negative. -largeNum :: Gen Int +largeNum :: (MonadGen m) => m Int largeNum = Hog.int $ Hog.linear (-100) 100 -- | Generates a random size for a wire so that it is not too small and not too -- large. -wireSize :: Gen Int +wireSize :: (MonadGen m) => m Int wireSize = Hog.int $ Hog.linear 2 100 -- | Generates a random range by using the 'wireSize' and 0 as the lower bound. -range :: Gen Range +range :: (MonadGen m) => m Range range = Range <$> fmap fromIntegral wireSize <*> pure 0 -- | Generate a random bit vector using 'largeNum'. -genBitVec :: Gen BitVec +genBitVec :: (MonadGen m) => m BitVec genBitVec = fmap fromIntegral largeNum -- | Return a random 'BinaryOperator'. This currently excludes 'BinDiv', @@ -202,7 +198,7 @@ genBitVec = fmap fromIntegral largeNum -- 'BinCNEq', because these are not synthesisable. 'BinPower' is also excluded -- because it can only be used in conjunction with base powers of 2 which is -- currently not enforced. -binOp :: Gen BinaryOperator +binOp :: (MonadGen m) => m BinaryOperator binOp = Hog.element [ BinPlus , BinMinus @@ -232,7 +228,7 @@ binOp = Hog.element ] -- | Generate a random 'UnaryOperator'. -unOp :: Gen UnaryOperator +unOp :: (MonadGen m) => m UnaryOperator unOp = Hog.element [ UnPlus , UnMinus @@ -248,7 +244,7 @@ unOp = Hog.element ] -- | Generate a random 'ConstExpr' by using the current context of 'Parameter'. -constExprWithContext :: [Parameter] -> ProbExpr -> Hog.Size -> Gen ConstExpr +constExprWithContext :: (MonadGen m) => [Parameter] -> ProbExpr -> Hog.Size -> m ConstExpr constExprWithContext ps prob size | size == 0 = Hog.frequency [ (prob ^. probExprNum, ConstNum <$> genBitVec) @@ -277,12 +273,12 @@ constExprWithContext ps prob size -- | The list of safe 'Expr', meaning that these will not recurse and will end -- the 'Expr' generation. -exprSafeList :: ProbExpr -> [(Int, Gen Expr)] +exprSafeList :: (MonadGen m) => ProbExpr -> [(Int, m Expr)] exprSafeList prob = [(prob ^. probExprNum, Number <$> genBitVec)] -- | List of 'Expr' that have the chance to recurse and will therefore not be -- used when the expression grows too large. -exprRecList :: ProbExpr -> (Hog.Size -> Gen Expr) -> [(Int, Gen Expr)] +exprRecList :: (MonadGen m) => ProbExpr -> (Hog.Size -> m Expr) -> [(Int, m Expr)] exprRecList prob subexpr = [ (prob ^. probExprNum, Number <$> genBitVec) , ( prob ^. probExprConcat @@ -298,7 +294,7 @@ exprRecList prob subexpr = -- | Select a random port from a list of ports and generate a safe bit selection -- for that port. -rangeSelect :: [Parameter] -> [Port] -> Gen Expr +rangeSelect :: (MonadGen m) => [Parameter] -> [Port] -> m Expr rangeSelect ps ports = do p <- Hog.element ports let s = calcRange ps (Just 32) $ _portSize p @@ -309,7 +305,7 @@ rangeSelect ps ports = do -- | Generate a random expression from the 'Context' with a guarantee that it -- will terminate using the list of safe 'Expr'. -exprWithContext :: ProbExpr -> [Parameter] -> [Port] -> Hog.Size -> Gen Expr +exprWithContext :: (MonadGen m) => ProbExpr -> [Parameter] -> [Port] -> Hog.Size -> m Expr exprWithContext prob ps [] n | n == 0 = Hog.frequency $ exprSafeList prob | n > 0 = Hog.frequency $ exprRecList prob subexpr | otherwise = exprWithContext prob ps [] 0 @@ -332,7 +328,7 @@ exprWithContext prob ps l n -- passed to it. someI :: Int -> StateGen a -> StateGen [a] someI m f = do - amount <- gen $ Hog.int (Hog.linear 1 m) + amount <- Hog.int (Hog.linear 1 m) replicateM amount f -- | Make a new name with a prefix and the current nameCounter. The nameCounter @@ -365,8 +361,8 @@ nextPort pt = do -- current context. newPort :: Identifier -> PortType -> StateGen Port newPort ident pt = do - p <- gen $ Port pt <$> Hog.bool <*> range <*> pure ident - contextVariables %= (fromPort p :) + p <- Port pt <$> Hog.bool <*> range <*> pure ident + variables %= (p :) return p -- | Generates an expression from variables that are currently in scope. @@ -374,10 +370,9 @@ scopedExpr :: StateGen Expr scopedExpr = do context <- get prob <- askProbability - gen - . Hog.sized - . exprWithContext (_probExpr prob) (_contextParameters context) - $ _portsFromContext context + Hog.sized + . exprWithContext (_probExpr prob) (_parameters context) + $ _variables context -- | Generates a random continuous assignment and assigns it to a random wire -- that is created. @@ -469,14 +464,16 @@ instantiate :: ModDecl -> StateGen ModItem instantiate (ModDecl i outP inP _ _) = do context <- get outs <- replicateM (length outP) (nextPort Wire) - ins <- take (length inpFixed) <$> Hog.shuffle (_portsFromContext context) + ins <- take (length inpFixed) <$> Hog.shuffle (context ^. variables) + insLit <- replicateM (length inpFixed - length ins) (Number <$> genBitVec) mapM_ (uncurry process) . zip (ins ^.. traverse . portName) $ inpFixed ^.. traverse . portSize ident <- makeIdentifier "modinst" vs <- _portsFromContext <$> get Hog.choice - [ return . ModInst i ident $ ModConn <$> toE (outs <> clkPort <> ins) + [ return . ModInst i ident $ ModConn <$> (toE (outs <> clkPort <> ins) <> insLit) , ModInst i ident <$> Hog.shuffle - (zipWith ModConnNamed (_portName <$> outP <> clkPort <> inpFixed) (toE $ outs <> clkPort <> ins)) + (zipWith ModConnNamed (view portName <$> outP <> clkPort <> inpFixed) + (toE (outs <> clkPort <> ins) <> insLit)) ] where toE ins = Id . _portName <$> ins @@ -509,7 +506,7 @@ instantiate (ModDecl i outP inP _ _) = do -- a module from a context or generating a new one. modInst :: StateGen ModItem modInst = do - prob <- lift ask + prob <- ask context <- get let maxMods = prob ^. configProperty . propMaxModules if length (_contextModules context) < maxMods @@ -534,7 +531,7 @@ modInst = do -- | Generate a random module item. modItem :: StateGen ModItem modItem = do - conf <- lift ask + conf <- ask let prob = conf ^. configProbability context <- get let defProb i = prob ^. probModItem . i @@ -559,7 +556,7 @@ constExpr :: StateGen ConstExpr constExpr = do prob <- askProbability context <- get - gen . Hog.sized $ constExprWithContext (context ^. contextParameters) + Hog.sized $ constExprWithContext (context ^. parameters) (prob ^. probExpr) -- | Generate a random 'Parameter' and assign it to a constant expression which @@ -600,8 +597,8 @@ moduleDef top = do mi <- Hog.list (Hog.linear 4 100) modItem ps <- Hog.list (Hog.linear 0 10) parameter context <- get - config <- lift ask - let (newPorts, local) = partition (`identElem` portList) $ _portsFromContext context + config <- ask + let (newPorts, local) = partition (`identElem` portList) $ _variables context let size = evalRange (_contextParameters context) 32 @@ -623,10 +620,10 @@ moduleDef top = do -- 'State' to keep track of the current Verilog code structure. procedural :: T.Text -> Config -> Gen Verilog procedural top config = do - (mainMod, st) <- Hog.resize num $ runReaderT - (runStateT (moduleDef (Just $ Identifier top)) context) - config - return . Verilog $ mainMod : st ^. contextModules + (mainMod, st) <- Hog.resize num $ runStateT + (Hog.distributeT (runReaderT (moduleDef (Just $ Identifier top)) config)) + context + return . Verilog $ mainMod : st ^. modules where context = Context [] [] [] 0 (confProp propStmntDepth) (confProp propModDepth) True diff --git a/src/VeriFuzz/Internal.hs b/src/Verismith/Internal.hs index c7105fc..b47c924 100644 --- a/src/VeriFuzz/Internal.hs +++ b/src/Verismith/Internal.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Internal +Module : Verismith.Internal Description : Shared high level code used in the other modules internally. Copyright : (c) 2018-2019, Yann Herklotz License : BSD-3 @@ -10,7 +10,7 @@ Portability : POSIX Shared high level code used in the other modules internally. -} -module VeriFuzz.Internal +module Verismith.Internal ( -- * Useful functions safe , showT diff --git a/src/Verismith/OptParser.hs b/src/Verismith/OptParser.hs new file mode 100644 index 0000000..a475e9a --- /dev/null +++ b/src/Verismith/OptParser.hs @@ -0,0 +1,262 @@ +module Verismith.OptParser + ( OptTool (..) + , Opts (..) + , opts + ) +where + +import Control.Applicative ((<|>)) +import Data.Text (Text) +import qualified Data.Text as T +import Options.Applicative (Mod (..), OptionFields (..), Parser (..), + ParserInfo (..), ReadM (..), (<**>)) +import qualified Options.Applicative as Opt +import Prelude hiding (FilePath (..)) +import Shelly (FilePath (..), fromText) +import Verismith.Config (SynthDescription (..), versionInfo) + +data OptTool = TYosys + | TXST + | TIcarus + +instance Show OptTool where + show TYosys = "yosys" + show TXST = "xst" + show TIcarus = "icarus" + +data Opts = Fuzz { fuzzOutput :: {-# UNPACK #-} !Text + , fuzzConfigFile :: !(Maybe FilePath) + , fuzzForced :: !Bool + , fuzzKeepAll :: !Bool + , fuzzNum :: {-# UNPACK #-} !Int + , fuzzNoSim :: !Bool + , fuzzNoEquiv :: !Bool + , fuzzNoReduction :: !Bool + } + | Generate { generateFilename :: !(Maybe FilePath) + , generateConfigFile :: !(Maybe FilePath) + } + | Parse { parseFilename :: {-# UNPACK #-} !FilePath + } + | Reduce { reduceFilename :: {-# UNPACK #-} !FilePath + , reduceTop :: {-# UNPACK #-} !Text + , reduceScript :: !(Maybe FilePath) + , reduceSynthesiserDesc :: ![SynthDescription] + , reduceRerun :: !Bool + } + | ConfigOpt { configOptWriteConfig :: !(Maybe FilePath) + , configOptConfigFile :: !(Maybe FilePath) + , configOptDoRandomise :: !Bool + } + +textOption :: Mod OptionFields String -> Parser Text +textOption = fmap T.pack . Opt.strOption + +optReader :: (String -> Maybe a) -> ReadM a +optReader f = Opt.eitherReader $ \arg -> case f arg of + Just a -> Right a + Nothing -> Left $ "Cannot parse option: " <> arg + +parseSynth :: String -> Maybe OptTool +parseSynth val | val == "yosys" = Just TYosys + | val == "xst" = Just TXST + | otherwise = Nothing + +parseSynthDesc :: String -> Maybe SynthDescription +parseSynthDesc val + | val == "yosys" = Just $ SynthDescription "yosys" Nothing Nothing Nothing + | val == "vivado" = Just $ SynthDescription "vivado" Nothing Nothing Nothing + | val == "xst" = Just $ SynthDescription "xst" Nothing Nothing Nothing + | val == "quartus" = Just + $ SynthDescription "quartus" Nothing Nothing Nothing + | val == "identity" = Just + $ SynthDescription "identity" Nothing Nothing Nothing + | otherwise = Nothing + +parseSim :: String -> Maybe OptTool +parseSim val | val == "icarus" = Just TIcarus + | otherwise = Nothing + +fuzzOpts :: Parser Opts +fuzzOpts = + Fuzz + <$> textOption + ( Opt.long "output" + <> Opt.short 'o' + <> Opt.metavar "DIR" + <> Opt.help "Output directory that the fuzz run takes place in." + <> Opt.showDefault + <> Opt.value "output") + <*> ( Opt.optional + . Opt.strOption + $ Opt.long "config" + <> Opt.short 'c' + <> Opt.metavar "FILE" + <> Opt.help "Config file for the current fuzz run.") + <*> (Opt.switch $ Opt.long "force" <> Opt.short 'f' <> Opt.help + "Overwrite the specified directory.") + <*> (Opt.switch $ Opt.long "keep" <> Opt.short 'k' <> Opt.help + "Keep all the directories.") + <*> ( Opt.option Opt.auto + $ Opt.long "num" + <> Opt.short 'n' + <> Opt.help "The number of fuzz runs that should be performed." + <> Opt.showDefault + <> Opt.value 1 + <> Opt.metavar "INT") + <*> (Opt.switch $ Opt.long "no-sim" <> Opt.help + "Do not run simulation on the output netlist.") + <*> (Opt.switch $ Opt.long "no-equiv" <> Opt.help + "Do not run an equivalence check on the output netlist.") + <*> (Opt.switch $ Opt.long "no-reduction" <> Opt.help + "Do not run reduction on a failed testcase.") + +genOpts :: Parser Opts +genOpts = + Generate + <$> ( Opt.optional + . Opt.strOption + $ Opt.long "output" + <> Opt.short 'o' + <> Opt.metavar "FILE" + <> Opt.help "Output to a verilog file instead." + ) + <*> ( Opt.optional + . Opt.strOption + $ Opt.long "config" + <> Opt.short 'c' + <> Opt.metavar "FILE" + <> Opt.help "Config file for the generation run." + ) + +parseOpts :: Parser Opts +parseOpts = Parse . fromText . T.pack <$> Opt.strArgument + (Opt.metavar "FILE" <> Opt.help "Verilog input file.") + +reduceOpts :: Parser Opts +reduceOpts = + Reduce + . fromText + . T.pack + <$> Opt.strArgument (Opt.metavar "FILE" <> Opt.help "Verilog input file.") + <*> textOption + ( Opt.short 't' + <> Opt.long "top" + <> Opt.metavar "TOP" + <> Opt.help "Name of top level module." + <> Opt.showDefault + <> Opt.value "top" + ) + <*> ( Opt.optional + . Opt.strOption + $ Opt.long "script" + <> Opt.metavar "SCRIPT" + <> Opt.help + "Script that determines if the current file is interesting, which is determined by the script returning 0." + ) + <*> ( Opt.many + . Opt.option (optReader parseSynthDesc) + $ Opt.short 's' + <> Opt.long "synth" + <> Opt.metavar "SYNTH" + <> Opt.help "Specify synthesiser to use." + ) + <*> ( Opt.switch + $ Opt.short 'r' + <> Opt.long "rerun" + <> Opt.help + "Only rerun the current synthesis file with all the synthesisers." + ) + +configOpts :: Parser Opts +configOpts = + ConfigOpt + <$> ( Opt.optional + . Opt.strOption + $ Opt.long "output" + <> Opt.short 'o' + <> Opt.metavar "FILE" + <> Opt.help "Output to a TOML Config file." + ) + <*> ( Opt.optional + . Opt.strOption + $ Opt.long "config" + <> Opt.short 'c' + <> Opt.metavar "FILE" + <> Opt.help "Config file for the current fuzz run." + ) + <*> ( Opt.switch + $ Opt.long "randomise" + <> Opt.short 'r' + <> Opt.help + "Randomise the given default config, or the default config by randomly switchin on and off options." + ) + +argparse :: Parser Opts +argparse = + Opt.hsubparser + ( Opt.command + "fuzz" + (Opt.info + fuzzOpts + (Opt.progDesc + "Run fuzzing on the specified simulators and synthesisers." + ) + ) + <> Opt.metavar "fuzz" + ) + <|> Opt.hsubparser + ( Opt.command + "generate" + (Opt.info + genOpts + (Opt.progDesc "Generate a random Verilog program.") + ) + <> Opt.metavar "generate" + ) + <|> Opt.hsubparser + ( Opt.command + "parse" + (Opt.info + parseOpts + (Opt.progDesc + "Parse a verilog file and output a pretty printed version." + ) + ) + <> Opt.metavar "parse" + ) + <|> Opt.hsubparser + ( Opt.command + "reduce" + (Opt.info + reduceOpts + (Opt.progDesc + "Reduce a Verilog file by rerunning the fuzzer on the file." + ) + ) + <> Opt.metavar "reduce" + ) + <|> Opt.hsubparser + ( Opt.command + "config" + (Opt.info + configOpts + (Opt.progDesc + "Print the current configuration of the fuzzer." + ) + ) + <> Opt.metavar "config" + ) + +version :: Parser (a -> a) +version = Opt.infoOption versionInfo $ mconcat + [Opt.long "version", Opt.short 'v', Opt.help "Show version information.", Opt.hidden] + +opts :: ParserInfo Opts +opts = Opt.info + (argparse <**> Opt.helper <**> version) + ( Opt.fullDesc + <> Opt.progDesc "Fuzz different simulators and synthesisers." + <> Opt.header + "Verismith - A hardware simulator and synthesiser Verilog fuzzer." + ) diff --git a/src/VeriFuzz/Reduce.hs b/src/Verismith/Reduce.hs index 61b7bba..a7ec3f8 100644 --- a/src/VeriFuzz/Reduce.hs +++ b/src/Verismith/Reduce.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Reduce +Module : Verismith.Reduce Description : Test case reducer implementation. Copyright : (c) 2019, Yann Herklotz License : GPL-3 @@ -13,7 +13,7 @@ Test case reducer implementation. {-# LANGUAGE RankNTypes #-} {-# LANGUAGE ScopedTypeVariables #-} -module VeriFuzz.Reduce +module Verismith.Reduce ( -- $strategy reduceWithScript , reduceSynth @@ -35,26 +35,26 @@ module VeriFuzz.Reduce ) where -import Control.Lens hiding ((<.>)) -import Control.Monad (void) -import Control.Monad.IO.Class (MonadIO, liftIO) -import Data.Foldable (foldrM) -import Data.List (nub) -import Data.List.NonEmpty (NonEmpty (..)) -import qualified Data.List.NonEmpty as NonEmpty -import Data.Maybe (mapMaybe) -import Data.Text (Text) -import Shelly ((<.>)) +import Control.Lens hiding ((<.>)) +import Control.Monad (void) +import Control.Monad.IO.Class (MonadIO, liftIO) +import Data.Foldable (foldrM) +import Data.List (nub) +import Data.List.NonEmpty (NonEmpty (..)) +import qualified Data.List.NonEmpty as NonEmpty +import Data.Maybe (mapMaybe) +import Data.Text (Text) +import Shelly ((<.>)) import qualified Shelly -import Shelly.Lifted (MonadSh, liftSh) -import VeriFuzz.Internal -import VeriFuzz.Result -import VeriFuzz.Sim -import VeriFuzz.Sim.Internal -import VeriFuzz.Verilog -import VeriFuzz.Verilog.AST -import VeriFuzz.Verilog.Mutate -import VeriFuzz.Verilog.Parser +import Shelly.Lifted (MonadSh, liftSh) +import Verismith.Internal +import Verismith.Result +import Verismith.Tool +import Verismith.Tool.Internal +import Verismith.Verilog +import Verismith.Verilog.AST +import Verismith.Verilog.Mutate +import Verismith.Verilog.Parser -- $strategy @@ -582,17 +582,18 @@ reduceWithScript top script file = do -- | Reduce a 'SourceInfo' using two 'Synthesiser' that are passed to it. reduceSynth :: (Synthesiser a, Synthesiser b, MonadSh m) - => a + => Shelly.FilePath + -> a -> b -> SourceInfo -> m SourceInfo -reduceSynth a b = reduce synth +reduceSynth datadir a b = reduce synth where synth src' = liftSh $ do r <- runResultT $ do runSynth a src' runSynth b src' - runEquiv a b src' + runEquiv datadir a b src' return $ case r of Fail EquivFail -> True Fail _ -> False diff --git a/src/VeriFuzz/Report.hs b/src/Verismith/Report.hs index 56fd062..196e891 100644 --- a/src/VeriFuzz/Report.hs +++ b/src/Verismith/Report.hs @@ -1,6 +1,6 @@ {-# LANGUAGE RankNTypes #-} {-| -Module : VeriFuzz.Report +Module : Verismith.Report Description : Generate a report from a fuzz run. Copyright : (c) 2019, Yann Herklotz Grave License : GPL-3 @@ -13,7 +13,7 @@ Generate a report from a fuzz run. {-# LANGUAGE TemplateHaskell #-} -module VeriFuzz.Report +module Verismith.Report ( SynthTool(..) , SynthStatus(..) , SynthResult(..) @@ -60,11 +60,11 @@ import Text.Blaze.Html (Html, (!)) import Text.Blaze.Html.Renderer.Text (renderHtml) import qualified Text.Blaze.Html5 as H import qualified Text.Blaze.Html5.Attributes as A -import VeriFuzz.Config -import VeriFuzz.Internal -import VeriFuzz.Result -import VeriFuzz.Sim -import VeriFuzz.Sim.Internal +import Verismith.Config +import Verismith.Internal +import Verismith.Result +import Verismith.Tool +import Verismith.Tool.Internal -- | Common type alias for synthesis results type UResult = Result Failed () @@ -192,9 +192,9 @@ instance Show SynthStatus where -- | The complete state that will be used during fuzzing, which contains the -- results from all the operations. data FuzzReport = FuzzReport { _fuzzDir :: !FilePath - , _synthResults :: ![SynthResult] - , _simResults :: ![SimResult] - , _synthStatus :: ![SynthStatus] + , _synthResults :: ![SynthResult] -- ^ Results of the equivalence check. + , _simResults :: ![SimResult] -- ^ Results of the simulation. + , _synthStatus :: ![SynthStatus] -- ^ Results of the synthesis step. , _fileLines :: {-# UNPACK #-} !Int , _synthTime :: !NominalDiffTime , _equivTime :: !NominalDiffTime @@ -316,7 +316,7 @@ fuzzStatus name (FuzzReport dir s1 s2 s3 sz t1 t2 t3) = H.tr $ do . ( H.a ! A.href ( H.textValue - $ toTextIgnore (dir </> fromText "index" <.> "html") + $ toTextIgnore (dir <.> "html") ) ) $ H.toHtml name diff --git a/src/VeriFuzz/Result.hs b/src/Verismith/Result.hs index 61b1452..d8efd2f 100644 --- a/src/VeriFuzz/Result.hs +++ b/src/Verismith/Result.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Result +Module : Verismith.Result Description : Result monadic type. Copyright : (c) 2019, Yann Herklotz Grave License : GPL-3 @@ -9,7 +9,7 @@ Portability : POSIX Result monadic type. This is nearly equivalent to the transformers 'Error' type, but to have more control this is reimplemented with the instances that are -needed in "VeriFuzz". +needed in "Verismith". -} {-# LANGUAGE FlexibleContexts #-} @@ -19,7 +19,7 @@ needed in "VeriFuzz". {-# LANGUAGE TypeFamilies #-} {-# LANGUAGE UndecidableInstances #-} -module VeriFuzz.Result +module Verismith.Result ( Result(..) , ResultT(..) , (<?>) diff --git a/src/VeriFuzz/Sim.hs b/src/Verismith/Tool.hs index 92d1bc4..7e41180 100644 --- a/src/VeriFuzz/Sim.hs +++ b/src/Verismith/Tool.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Sim +Module : Verismith.Tool Description : Simulator implementations. Copyright : (c) 2019, Yann Herklotz Grave License : GPL-3 @@ -10,7 +10,7 @@ Portability : POSIX Simulator implementations. -} -module VeriFuzz.Sim +module Verismith.Tool ( -- * Simulators -- ** Icarus @@ -42,10 +42,10 @@ module VeriFuzz.Sim ) where -import VeriFuzz.Sim.Icarus -import VeriFuzz.Sim.Identity -import VeriFuzz.Sim.Internal -import VeriFuzz.Sim.Quartus -import VeriFuzz.Sim.Vivado -import VeriFuzz.Sim.XST -import VeriFuzz.Sim.Yosys +import Verismith.Tool.Icarus +import Verismith.Tool.Identity +import Verismith.Tool.Internal +import Verismith.Tool.Quartus +import Verismith.Tool.Vivado +import Verismith.Tool.XST +import Verismith.Tool.Yosys diff --git a/src/VeriFuzz/Sim/Icarus.hs b/src/Verismith/Tool/Icarus.hs index 9041d14..9d4281f 100644 --- a/src/VeriFuzz/Sim/Icarus.hs +++ b/src/Verismith/Tool/Icarus.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Sim.Icarus +Module : Verismith.Tool.Icarus Description : Icarus verilog module. Copyright : (c) 2018-2019, Yann Herklotz License : BSD-3 @@ -10,42 +10,42 @@ Portability : POSIX Icarus verilog module. -} -module VeriFuzz.Sim.Icarus +module Verismith.Tool.Icarus ( Icarus(..) , defaultIcarus , runSimIc ) where -import Control.DeepSeq (NFData, rnf, rwhnf) +import Control.DeepSeq (NFData, rnf, rwhnf) import Control.Lens -import Control.Monad (void) -import Crypto.Hash (Digest, hash) -import Crypto.Hash.Algorithms (SHA256) -import Data.Binary (encode) +import Control.Monad (void) +import Crypto.Hash (Digest, hash) +import Crypto.Hash.Algorithms (SHA256) +import Data.Binary (encode) import Data.Bits -import qualified Data.ByteArray as BA (convert) -import Data.ByteString (ByteString) -import qualified Data.ByteString as B -import Data.ByteString.Lazy (toStrict) -import qualified Data.ByteString.Lazy as L (ByteString) -import Data.Char (digitToInt) -import Data.Foldable (fold) -import Data.List (transpose) -import Data.Maybe (listToMaybe) -import Data.Text (Text) -import qualified Data.Text as T -import Numeric (readInt) -import Prelude hiding (FilePath) +import qualified Data.ByteArray as BA (convert) +import Data.ByteString (ByteString) +import qualified Data.ByteString as B +import Data.ByteString.Lazy (toStrict) +import qualified Data.ByteString.Lazy as L (ByteString) +import Data.Char (digitToInt) +import Data.Foldable (fold) +import Data.List (transpose) +import Data.Maybe (listToMaybe) +import Data.Text (Text) +import qualified Data.Text as T +import Numeric (readInt) +import Prelude hiding (FilePath) import Shelly -import Shelly.Lifted (liftSh) -import VeriFuzz.Sim.Internal -import VeriFuzz.Sim.Template -import VeriFuzz.Verilog.AST -import VeriFuzz.Verilog.BitVec -import VeriFuzz.Verilog.CodeGen -import VeriFuzz.Verilog.Internal -import VeriFuzz.Verilog.Mutate +import Shelly.Lifted (liftSh) +import Verismith.Tool.Internal +import Verismith.Tool.Template +import Verismith.Verilog.AST +import Verismith.Verilog.BitVec +import Verismith.Verilog.CodeGen +import Verismith.Verilog.Internal +import Verismith.Verilog.Mutate data Icarus = Icarus { icarusPath :: FilePath , vvpPath :: FilePath @@ -133,15 +133,16 @@ fromBytes = B.foldl' f 0 where f a b = a `shiftL` 8 .|. fromIntegral b runSimIc :: (Synthesiser b) - => Icarus + => FilePath + -> Icarus -> b -> SourceInfo -> [ByteString] -> ResultSh ByteString -runSimIc sim1 synth1 srcInfo bss = do +runSimIc datadir sim1 synth1 srcInfo bss = do dir <- liftSh pwd let top = srcInfo ^. mainModule - let inConcat = (RegConcat (Id . _portName <$> (top ^. modInPorts))) + let inConcat = (RegConcat . filter filterClk $ (Id . fromPort <$> (top ^. modInPorts))) let tb = instantiateMod top $ ModDecl "testbench" @@ -170,7 +171,7 @@ runSimIc sim1 synth1 srcInfo bss = do ] [] - liftSh . writefile "testbench.v" $ icarusTestbench (Verilog [tb]) synth1 + liftSh . writefile "testbench.v" $ icarusTestbench datadir (Verilog [tb]) synth1 liftSh $ exe dir "icarus" "iverilog" ["-o", "main", "testbench.v"] liftSh $ B.take 8 @@ -186,3 +187,5 @@ runSimIc sim1 synth1 srcInfo bss = do ) where exe dir name e = void . errExit False . logCommand dir name . timeout e + filterClk (Id "clk") = False + filterClk (Id _) = True diff --git a/src/VeriFuzz/Sim/Identity.hs b/src/Verismith/Tool/Identity.hs index bfa99f5..93b05d5 100644 --- a/src/VeriFuzz/Sim/Identity.hs +++ b/src/Verismith/Tool/Identity.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Sim.Identity +Module : Verismith.Tool.Identity Description : The identity simulator and synthesiser. Copyright : (c) 2019, Yann Herklotz Grave License : GPL-3 @@ -10,20 +10,20 @@ Portability : POSIX The identity simulator and synthesiser. -} -module VeriFuzz.Sim.Identity +module Verismith.Tool.Identity ( Identity(..) , defaultIdentity ) where -import Control.DeepSeq (NFData, rnf, rwhnf) -import Data.Text (Text, unpack) -import Prelude hiding (FilePath) -import Shelly (FilePath) -import Shelly.Lifted (writefile) -import VeriFuzz.Sim.Internal -import VeriFuzz.Verilog.AST -import VeriFuzz.Verilog.CodeGen +import Control.DeepSeq (NFData, rnf, rwhnf) +import Data.Text (Text, unpack) +import Prelude hiding (FilePath) +import Shelly (FilePath) +import Shelly.Lifted (writefile) +import Verismith.Tool.Internal +import Verismith.Verilog.AST +import Verismith.Verilog.CodeGen data Identity = Identity { identityDesc :: {-# UNPACK #-} !Text , identityOutput :: {-# UNPACK #-} !FilePath diff --git a/src/VeriFuzz/Sim/Internal.hs b/src/Verismith/Tool/Internal.hs index f5351c7..c2e3a0c 100644 --- a/src/VeriFuzz/Sim/Internal.hs +++ b/src/Verismith/Tool/Internal.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Sim.Internal +Module : Verismith.Tool.Internal Description : Class of the simulator. Copyright : (c) 2018-2019, Yann Herklotz License : BSD-3 @@ -12,7 +12,7 @@ Class of the simulator and the synthesize tool. {-# LANGUAGE DeriveFunctor #-} -module VeriFuzz.Sim.Internal +module Verismith.Tool.Internal ( ResultSh , resultSh , Tool(..) @@ -54,9 +54,9 @@ import Prelude hiding (FilePath) import Shelly import Shelly.Lifted (MonadSh, liftSh) import System.FilePath.Posix (takeBaseName) -import VeriFuzz.Internal -import VeriFuzz.Result -import VeriFuzz.Verilog.AST +import Verismith.Internal +import Verismith.Result +import Verismith.Verilog.AST -- | Tool class. class Tool a where @@ -100,7 +100,7 @@ renameSource :: (Synthesiser a) => a -> SourceInfo -> SourceInfo renameSource a src = src & infoSrc . _Wrapped . traverse . modId . _Wrapped %~ (<> toText a) --- | Type synonym for a 'ResultT' that will be used throughout 'VeriFuzz'. This +-- | Type synonym for a 'ResultT' that will be used throughout 'Verismith'. This -- has instances for 'MonadSh' and 'MonadIO' if the 'Monad' it is parametrised -- with also has those instances. type ResultSh = ResultT Failed Sh @@ -146,7 +146,7 @@ replaceMods fp t (SourceInfo _ src) = rootPath :: Sh FilePath rootPath = do current <- pwd - maybe current fromText <$> get_env "VERIFUZZ_ROOT" + maybe current fromText <$> get_env "VERISMITH_ROOT" timeout :: FilePath -> [Text] -> Sh Text timeout = command1 "timeout" ["300"] . toTextIgnore @@ -170,7 +170,7 @@ logger t = do fn <- pwd currentTime <- liftIO getZonedTime echo - $ "VeriFuzz " + $ "Verismith " <> T.pack (formatTime defaultTimeLocale "%H:%M:%S " currentTime) <> bname fn <> " - " diff --git a/src/VeriFuzz/Sim/Quartus.hs b/src/Verismith/Tool/Quartus.hs index 254bfa5..109d46c 100644 --- a/src/VeriFuzz/Sim/Quartus.hs +++ b/src/Verismith/Tool/Quartus.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Sim.Quartus +Module : Verismith.Tool.Quartus Description : Quartus synthesiser implementation. Copyright : (c) 2019, Yann Herklotz Grave License : GPL-3 @@ -10,20 +10,20 @@ Portability : POSIX Quartus synthesiser implementation. -} -module VeriFuzz.Sim.Quartus +module Verismith.Tool.Quartus ( Quartus(..) , defaultQuartus ) where -import Control.DeepSeq (NFData, rnf, rwhnf) -import Data.Text (Text, unpack) -import Prelude hiding (FilePath) +import Control.DeepSeq (NFData, rnf, rwhnf) +import Data.Text (Text, unpack) +import Prelude hiding (FilePath) import Shelly -import Shelly.Lifted (liftSh) -import VeriFuzz.Sim.Internal -import VeriFuzz.Verilog.AST -import VeriFuzz.Verilog.CodeGen +import Shelly.Lifted (liftSh) +import Verismith.Tool.Internal +import Verismith.Verilog.AST +import Verismith.Verilog.CodeGen data Quartus = Quartus { quartusBin :: !(Maybe FilePath) , quartusDesc :: {-# UNPACK #-} !Text diff --git a/src/VeriFuzz/Sim/Template.hs b/src/Verismith/Tool/Template.hs index 9b8ee9f..d02daf8 100644 --- a/src/VeriFuzz/Sim/Template.hs +++ b/src/Verismith/Tool/Template.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Sim.Template +Module : Verismith.Tool.Template Description : Template file for different configuration files Copyright : (c) 2019, Yann Herklotz License : GPL-3 @@ -12,7 +12,7 @@ Template file for different configuration files. {-# LANGUAGE QuasiQuotes #-} -module VeriFuzz.Sim.Template +module Verismith.Tool.Template ( yosysSatConfig , yosysSimConfig , xstSynthConfig @@ -22,15 +22,15 @@ module VeriFuzz.Sim.Template ) where -import Control.Lens ((^..)) -import Data.Text (Text) -import qualified Data.Text as T -import Prelude hiding (FilePath) +import Control.Lens ((^..)) +import Data.Text (Text) +import qualified Data.Text as T +import Prelude hiding (FilePath) import Shelly -import Text.Shakespeare.Text (st) -import VeriFuzz.Sim.Internal -import VeriFuzz.Verilog.AST -import VeriFuzz.Verilog.CodeGen +import Text.Shakespeare.Text (st) +import Verismith.Tool.Internal +import Verismith.Verilog.AST +import Verismith.Verilog.CodeGen rename :: Text -> [Text] -> Text rename end entries = @@ -89,8 +89,8 @@ write_verilog -force #{outf} |] -- brittany-disable-next-binding -sbyConfig :: (Synthesiser a, Synthesiser b) => a -> b -> SourceInfo -> Text -sbyConfig sim1 sim2 (SourceInfo top _) = [st|[options] +sbyConfig :: (Synthesiser a, Synthesiser b) => FilePath -> a -> b -> SourceInfo -> Text +sbyConfig datadir sim1 sim2 (SourceInfo top _) = [st|[options] multiclock on mode prove @@ -115,19 +115,21 @@ top.v depList = T.intercalate "\n" $ toTextIgnore - . (fromText "data" </>) + . (datadir </> fromText "data" </>) . fromText <$> deps readL = T.intercalate "\n" $ mappend "read -formal " <$> deps -icarusTestbench :: (Synthesiser a) => Verilog -> a -> Text -icarusTestbench t synth1 = [st| -`include "data/cells_cmos.v" -`include "data/cells_cyclone_v.v" -`include "data/cells_verific.v" -`include "data/cells_xilinx_7.v" -`include "data/cells_yosys.v" +icarusTestbench :: (Synthesiser a) => FilePath -> Verilog -> a -> Text +icarusTestbench datadir t synth1 = [st| +`include "#{ddir}/data/cells_cmos.v" +`include "#{ddir}/data/cells_cyclone_v.v" +`include "#{ddir}/data/cells_verific.v" +`include "#{ddir}/data/cells_xilinx_7.v" +`include "#{ddir}/data/cells_yosys.v" `include "#{toTextIgnore $ synthOutput synth1}" #{genSource t} |] + where + ddir = toTextIgnore datadir diff --git a/src/VeriFuzz/Sim/Vivado.hs b/src/Verismith/Tool/Vivado.hs index 4ddb048..272311e 100644 --- a/src/VeriFuzz/Sim/Vivado.hs +++ b/src/Verismith/Tool/Vivado.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Sim.Vivado +Module : Verismith.Tool.Vivado Description : Vivado Synthesiser implementation. Copyright : (c) 2019, Yann Herklotz Grave License : GPL-3 @@ -10,21 +10,21 @@ Portability : POSIX Vivado Synthesiser implementation. -} -module VeriFuzz.Sim.Vivado +module Verismith.Tool.Vivado ( Vivado(..) , defaultVivado ) where -import Control.DeepSeq (NFData, rnf, rwhnf) -import Data.Text (Text, unpack) -import Prelude hiding (FilePath) +import Control.DeepSeq (NFData, rnf, rwhnf) +import Data.Text (Text, unpack) +import Prelude hiding (FilePath) import Shelly -import Shelly.Lifted (liftSh) -import VeriFuzz.Sim.Internal -import VeriFuzz.Sim.Template -import VeriFuzz.Verilog.AST -import VeriFuzz.Verilog.CodeGen +import Shelly.Lifted (liftSh) +import Verismith.Tool.Internal +import Verismith.Tool.Template +import Verismith.Verilog.AST +import Verismith.Verilog.CodeGen data Vivado = Vivado { vivadoBin :: !(Maybe FilePath) , vivadoDesc :: {-# UNPACK #-} !Text diff --git a/src/VeriFuzz/Sim/XST.hs b/src/Verismith/Tool/XST.hs index 86db667..c713e0b 100644 --- a/src/VeriFuzz/Sim/XST.hs +++ b/src/Verismith/Tool/XST.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Sim.XST +Module : Verismith.Tool.XST Description : XST (ise) simulator implementation. Copyright : (c) 2018-2019, Yann Herklotz License : BSD-3 @@ -12,22 +12,22 @@ XST (ise) simulator implementation. {-# LANGUAGE QuasiQuotes #-} -module VeriFuzz.Sim.XST +module Verismith.Tool.XST ( XST(..) , defaultXST ) where -import Control.DeepSeq (NFData, rnf, rwhnf) -import Data.Text (Text, unpack) -import Prelude hiding (FilePath) +import Control.DeepSeq (NFData, rnf, rwhnf) +import Data.Text (Text, unpack) +import Prelude hiding (FilePath) import Shelly -import Shelly.Lifted (liftSh) -import Text.Shakespeare.Text (st) -import VeriFuzz.Sim.Internal -import VeriFuzz.Sim.Template -import VeriFuzz.Verilog.AST -import VeriFuzz.Verilog.CodeGen +import Shelly.Lifted (liftSh) +import Text.Shakespeare.Text (st) +import Verismith.Tool.Internal +import Verismith.Tool.Template +import Verismith.Verilog.AST +import Verismith.Verilog.CodeGen data XST = XST { xstBin :: !(Maybe FilePath) , xstDesc :: {-# UNPACK #-} !Text diff --git a/src/VeriFuzz/Sim/Yosys.hs b/src/Verismith/Tool/Yosys.hs index 8c73b86..afbffe9 100644 --- a/src/VeriFuzz/Sim/Yosys.hs +++ b/src/Verismith/Tool/Yosys.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Sim.Yosys +Module : Verismith.Tool.Yosys Description : Yosys simulator implementation. Copyright : (c) 2018-2019, Yann Herklotz License : BSD-3 @@ -12,7 +12,7 @@ Yosys simulator implementation. {-# LANGUAGE QuasiQuotes #-} -module VeriFuzz.Sim.Yosys +module Verismith.Tool.Yosys ( Yosys(..) , defaultYosys , runEquiv @@ -20,20 +20,20 @@ module VeriFuzz.Sim.Yosys ) where -import Control.DeepSeq (NFData, rnf, rwhnf) +import Control.DeepSeq (NFData, rnf, rwhnf) import Control.Lens -import Control.Monad (void) -import Data.Text (Text, unpack) -import Prelude hiding (FilePath) +import Control.Monad (void) +import Data.Text (Text, unpack) +import Prelude hiding (FilePath) import Shelly -import Shelly.Lifted (liftSh) -import Text.Shakespeare.Text (st) -import VeriFuzz.Result -import VeriFuzz.Sim.Internal -import VeriFuzz.Sim.Template -import VeriFuzz.Verilog.AST -import VeriFuzz.Verilog.CodeGen -import VeriFuzz.Verilog.Mutate +import Shelly.Lifted (liftSh) +import Text.Shakespeare.Text (st) +import Verismith.Result +import Verismith.Tool.Internal +import Verismith.Tool.Template +import Verismith.Verilog.AST +import Verismith.Verilog.CodeGen +import Verismith.Verilog.Mutate data Yosys = Yosys { yosysBin :: !(Maybe FilePath) , yosysDesc :: {-# UNPACK #-} !Text @@ -102,8 +102,8 @@ runEquivYosys yosys sim1 sim2 srcInfo = do where checkFile = fromText [st|test.#{toText sim1}.#{toText sim2}.ys|] runEquiv - :: (Synthesiser a, Synthesiser b) => a -> b -> SourceInfo -> ResultSh () -runEquiv sim1 sim2 srcInfo = do + :: (Synthesiser a, Synthesiser b) => FilePath -> a -> b -> SourceInfo -> ResultSh () +runEquiv datadir sim1 sim2 srcInfo = do dir <- liftSh pwd liftSh $ do writefile "top.v" @@ -114,7 +114,7 @@ runEquiv sim1 sim2 srcInfo = do ^. mainModule replaceMods (synthOutput sim1) "_1" srcInfo replaceMods (synthOutput sim2) "_2" srcInfo - writefile "proof.sby" $ sbyConfig sim1 sim2 srcInfo + writefile "proof.sby" $ sbyConfig datadir sim1 sim2 srcInfo e <- liftSh $ do exe dir "symbiyosys" "sby" ["-f", "proof.sby"] lastExitCode diff --git a/src/VeriFuzz/Verilog.hs b/src/Verismith/Verilog.hs index 4b5029c..f3d9e85 100644 --- a/src/VeriFuzz/Verilog.hs +++ b/src/Verismith/Verilog.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Verilog +Module : Verismith.Verilog Description : Verilog implementation with random generation and mutations. Copyright : (c) 2019, Yann Herklotz Grave License : GPL-3 @@ -12,7 +12,7 @@ Verilog implementation with random generation and mutations. {-# LANGUAGE QuasiQuotes #-} -module VeriFuzz.Verilog +module Verismith.Verilog ( SourceInfo(..) , Verilog(..) , parseVerilog @@ -100,7 +100,7 @@ module VeriFuzz.Verilog ) where -import VeriFuzz.Verilog.AST -import VeriFuzz.Verilog.CodeGen -import VeriFuzz.Verilog.Parser -import VeriFuzz.Verilog.Quote +import Verismith.Verilog.AST +import Verismith.Verilog.CodeGen +import Verismith.Verilog.Parser +import Verismith.Verilog.Quote diff --git a/src/VeriFuzz/Verilog/AST.hs b/src/Verismith/Verilog/AST.hs index a85c365..699d87a 100644 --- a/src/VeriFuzz/Verilog/AST.hs +++ b/src/Verismith/Verilog/AST.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Verilog.AST +Module : Verismith.Verilog.AST Description : Definition of the Verilog AST types. Copyright : (c) 2018-2019, Yann Herklotz License : BSD-3 @@ -22,7 +22,7 @@ Defines the types to build a Verilog AST. {-# LANGUAGE TemplateHaskell #-} {-# LANGUAGE TypeFamilies #-} -module VeriFuzz.Verilog.AST +module Verismith.Verilog.AST ( -- * Top level types SourceInfo(..) , infoTop @@ -150,7 +150,7 @@ import Data.String (IsString, fromString) import Data.Text (Text, pack) import Data.Traversable (sequenceA) import GHC.Generics (Generic) -import VeriFuzz.Verilog.BitVec +import Verismith.Verilog.BitVec -- | Identifier in Verilog. This is just a string of characters that can either -- be lowercase and uppercase for now. This might change in the future though, diff --git a/src/VeriFuzz/Verilog/BitVec.hs b/src/Verismith/Verilog/BitVec.hs index 0cc9eb3..bc594a3 100644 --- a/src/VeriFuzz/Verilog/BitVec.hs +++ b/src/Verismith/Verilog/BitVec.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Verilog.BitVec +Module : Verismith.Verilog.BitVec Description : Unsigned BitVec implementation. Copyright : (c) 2019, Yann Herklotz Grave License : GPL-3 @@ -17,7 +17,7 @@ Unsigned BitVec implementation. {-# LANGUAGE DeriveGeneric #-} {-# LANGUAGE DeriveTraversable #-} -module VeriFuzz.Verilog.BitVec +module Verismith.Verilog.BitVec ( BitVecF(..) , BitVec , bitVec diff --git a/src/VeriFuzz/Verilog/CodeGen.hs b/src/Verismith/Verilog/CodeGen.hs index 56e2819..842394d 100644 --- a/src/VeriFuzz/Verilog/CodeGen.hs +++ b/src/Verismith/Verilog/CodeGen.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Verilog.CodeGen +Module : Verismith.Verilog.CodeGen Description : Code generation for Verilog AST. Copyright : (c) 2018-2019, Yann Herklotz License : BSD-3 @@ -8,13 +8,13 @@ Stability : experimental Portability : POSIX This module generates the code from the Verilog AST defined in -"VeriFuzz.Verilog.AST". +"Verismith.Verilog.AST". -} {-# LANGUAGE DeriveDataTypeable #-} {-# LANGUAGE FlexibleInstances #-} -module VeriFuzz.Verilog.CodeGen +module Verismith.Verilog.CodeGen ( -- * Code Generation GenVerilog(..) , Source(..) @@ -28,9 +28,9 @@ import Data.Text (Text) import qualified Data.Text as T import Data.Text.Prettyprint.Doc import Numeric (showHex) -import VeriFuzz.Internal hiding (comma) -import VeriFuzz.Verilog.AST -import VeriFuzz.Verilog.BitVec +import Verismith.Internal hiding (comma) +import Verismith.Verilog.AST +import Verismith.Verilog.BitVec -- | 'Source' class which determines that source code is able to be generated -- from the data structure using 'genSource'. This will be stored in 'Text' and @@ -45,7 +45,7 @@ defMap = maybe semi statement -- | Convert the 'Verilog' type to 'Text' so that it can be rendered. verilogSrc :: Verilog -> Doc a -verilogSrc (Verilog modules) = vsep . punctuate line $ moduleDecl <$> modules +verilogSrc (Verilog modules) = vsep . ("// -*- mode: verilog -*-" :) . punctuate line $ moduleDecl <$> modules -- | Generate the 'ModDecl' for a module and convert it to 'Text'. moduleDecl :: ModDecl -> Doc a diff --git a/src/VeriFuzz/Verilog/Eval.hs b/src/Verismith/Verilog/Eval.hs index c802267..cbc2563 100644 --- a/src/VeriFuzz/Verilog/Eval.hs +++ b/src/Verismith/Verilog/Eval.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Verilog.Eval +Module : Verismith.Verilog.Eval Description : Evaluation of Verilog expressions and statements. Copyright : (c) 2019, Yann Herklotz Grave License : GPL-3 @@ -10,18 +10,18 @@ Portability : POSIX Evaluation of Verilog expressions and statements. -} -module VeriFuzz.Verilog.Eval +module Verismith.Verilog.Eval ( evaluateConst , resize ) where import Data.Bits -import Data.Foldable (fold) -import Data.Functor.Foldable hiding (fold) -import Data.Maybe (listToMaybe) -import VeriFuzz.Verilog.AST -import VeriFuzz.Verilog.BitVec +import Data.Foldable (fold) +import Data.Functor.Foldable hiding (fold) +import Data.Maybe (listToMaybe) +import Verismith.Verilog.AST +import Verismith.Verilog.BitVec type Bindings = [Parameter] diff --git a/src/VeriFuzz/Verilog/Internal.hs b/src/Verismith/Verilog/Internal.hs index 42eb4e2..b3bf07a 100644 --- a/src/VeriFuzz/Verilog/Internal.hs +++ b/src/Verismith/Verilog/Internal.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Verilog.Internal +Module : Verismith.Verilog.Internal Description : Defaults and common functions. Copyright : (c) 2018-2019, Yann Herklotz License : BSD-3 @@ -10,7 +10,7 @@ Portability : POSIX Defaults and common functions. -} -module VeriFuzz.Verilog.Internal +module Verismith.Verilog.Internal ( regDecl , wireDecl , emptyMod @@ -29,8 +29,8 @@ module VeriFuzz.Verilog.Internal where import Control.Lens -import Data.Text (Text) -import VeriFuzz.Verilog.AST +import Data.Text (Text) +import Verismith.Verilog.AST regDecl :: Identifier -> ModItem regDecl i = Decl Nothing (Port Reg False (Range 1 0) i) Nothing diff --git a/src/VeriFuzz/Verilog/Lex.x b/src/Verismith/Verilog/Lex.x index cc67ecc..9892714 100644 --- a/src/VeriFuzz/Verilog/Lex.x +++ b/src/Verismith/Verilog/Lex.x @@ -1,11 +1,11 @@ -- -*- haskell -*- { {-# OPTIONS_GHC -w #-} -module VeriFuzz.Verilog.Lex +module Verismith.Verilog.Lex ( alexScanTokens ) where -import VeriFuzz.Verilog.Token +import Verismith.Verilog.Token } diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/Verismith/Verilog/Mutate.hs index 2e88859..44a502a 100644 --- a/src/VeriFuzz/Verilog/Mutate.hs +++ b/src/Verismith/Verilog/Mutate.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Verilog.Mutate +Module : Verismith.Verilog.Mutate Description : Functions to mutate the Verilog AST. Copyright : (c) 2018-2019, Yann Herklotz License : BSD-3 @@ -7,13 +7,13 @@ Maintainer : yann [at] yannherklotz [dot] com Stability : experimental Portability : POSIX -Functions to mutate the Verilog AST from "VeriFuzz.Verilog.AST" to generate more +Functions to mutate the Verilog AST from "Verismith.Verilog.AST" to generate more random patterns, such as nesting wires instead of creating new ones. -} {-# LANGUAGE FlexibleInstances #-} -module VeriFuzz.Verilog.Mutate +module Verismith.Verilog.Mutate ( Mutate(..) , inPort , findAssign @@ -40,16 +40,16 @@ module VeriFuzz.Verilog.Mutate where import Control.Lens -import Data.Foldable (fold) -import Data.Maybe (catMaybes, fromMaybe) -import Data.Text (Text) -import qualified Data.Text as T -import VeriFuzz.Circuit.Internal -import VeriFuzz.Internal -import VeriFuzz.Verilog.AST -import VeriFuzz.Verilog.BitVec -import VeriFuzz.Verilog.CodeGen -import VeriFuzz.Verilog.Internal +import Data.Foldable (fold) +import Data.Maybe (catMaybes, fromMaybe) +import Data.Text (Text) +import qualified Data.Text as T +import Verismith.Circuit.Internal +import Verismith.Internal +import Verismith.Verilog.AST +import Verismith.Verilog.BitVec +import Verismith.Verilog.CodeGen +import Verismith.Verilog.Internal class Mutate a where mutExpr :: (Expr -> Expr) -> a -> a @@ -209,7 +209,7 @@ allVars m = <> (m ^.. modInPorts . traverse . portName) -- $setup --- >>> import VeriFuzz.Verilog.CodeGen +-- >>> import Verismith.Verilog.CodeGen -- >>> let m = (ModDecl (Identifier "m") [Port Wire False 5 (Identifier "y")] [Port Wire False 5 "x"] [] []) -- >>> let main = (ModDecl "main" [] [] [] []) diff --git a/src/VeriFuzz/Verilog/Parser.hs b/src/Verismith/Verilog/Parser.hs index c08ebcd..a6eaf24 100644 --- a/src/VeriFuzz/Verilog/Parser.hs +++ b/src/Verismith/Verilog/Parser.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Verilog.Parser +Module : Verismith.Verilog.Parser Description : Minimal Verilog parser to reconstruct the AST. Copyright : (c) 2019, Yann Herklotz License : GPL-3 @@ -11,7 +11,7 @@ Minimal Verilog parser to reconstruct the AST. This parser does not support the whole Verilog syntax, as the AST does not support it either. -} -module VeriFuzz.Verilog.Parser +module Verismith.Verilog.Parser ( -- * Parser parseVerilog , parseVerilogFile @@ -26,25 +26,25 @@ module VeriFuzz.Verilog.Parser where import Control.Lens -import Control.Monad (void) -import Data.Bifunctor (bimap) +import Control.Monad (void) +import Data.Bifunctor (bimap) import Data.Bits -import Data.Functor (($>)) -import Data.Functor.Identity (Identity) -import Data.List (isInfixOf, isPrefixOf, null) -import Data.List.NonEmpty (NonEmpty (..)) -import Data.Text (Text) -import qualified Data.Text as T -import qualified Data.Text.IO as T -import Text.Parsec hiding (satisfy) +import Data.Functor (($>)) +import Data.Functor.Identity (Identity) +import Data.List (isInfixOf, isPrefixOf, null) +import Data.List.NonEmpty (NonEmpty (..)) +import Data.Text (Text) +import qualified Data.Text as T +import qualified Data.Text.IO as T +import Text.Parsec hiding (satisfy) import Text.Parsec.Expr -import VeriFuzz.Internal -import VeriFuzz.Verilog.AST -import VeriFuzz.Verilog.BitVec -import VeriFuzz.Verilog.Internal -import VeriFuzz.Verilog.Lex -import VeriFuzz.Verilog.Preprocess -import VeriFuzz.Verilog.Token +import Verismith.Internal +import Verismith.Verilog.AST +import Verismith.Verilog.BitVec +import Verismith.Verilog.Internal +import Verismith.Verilog.Lex +import Verismith.Verilog.Preprocess +import Verismith.Verilog.Token type Parser = Parsec [Token] () diff --git a/src/VeriFuzz/Verilog/Preprocess.hs b/src/Verismith/Verilog/Preprocess.hs index c783ac5..91356f1 100644 --- a/src/VeriFuzz/Verilog/Preprocess.hs +++ b/src/Verismith/Verilog/Preprocess.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Verilog.Preprocess +Module : Verismith.Verilog.Preprocess Description : Simple preprocessor for `define and comments. Copyright : (c) 2011-2015 Tom Hawkins, 2019 Yann Herklotz License : GPL-3 @@ -14,7 +14,7 @@ The code is from https://github.com/tomahawkins/verilog. Edits to the original code are warning fixes and formatting changes. -} -module VeriFuzz.Verilog.Preprocess +module Verismith.Verilog.Preprocess ( uncomment , preprocess ) diff --git a/src/VeriFuzz/Verilog/Quote.hs b/src/Verismith/Verilog/Quote.hs index c6d3e3c..879b8fd 100644 --- a/src/VeriFuzz/Verilog/Quote.hs +++ b/src/Verismith/Verilog/Quote.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Verilog.Quote +Module : Verismith.Verilog.Quote Description : QuasiQuotation for verilog code in Haskell. Copyright : (c) 2019, Yann Herklotz Grave License : GPL-3 @@ -12,7 +12,7 @@ QuasiQuotation for verilog code in Haskell. {-# LANGUAGE TemplateHaskell #-} -module VeriFuzz.Verilog.Quote +module Verismith.Verilog.Quote ( verilog ) where @@ -22,7 +22,7 @@ import qualified Data.Text as T import qualified Language.Haskell.TH as TH import Language.Haskell.TH.Quote import Language.Haskell.TH.Syntax -import VeriFuzz.Verilog.Parser +import Verismith.Verilog.Parser liftDataWithText :: Data a => a -> Q Exp liftDataWithText = dataToExpQ $ fmap liftText . cast diff --git a/src/VeriFuzz/Verilog/Token.hs b/src/Verismith/Verilog/Token.hs index d69f0b3..b303e18 100644 --- a/src/VeriFuzz/Verilog/Token.hs +++ b/src/Verismith/Verilog/Token.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Verilog.Token +Module : Verismith.Verilog.Token Description : Tokens for Verilog parsing. Copyright : (c) 2019, Yann Herklotz Grave License : GPL-3 @@ -10,7 +10,7 @@ Portability : POSIX Tokens for Verilog parsing. -} -module VeriFuzz.Verilog.Token +module Verismith.Verilog.Token ( Token(..) , TokenName(..) , Position(..) |