diff options
Diffstat (limited to 'src')
34 files changed, 290 insertions, 290 deletions
diff --git a/src/VeriFuzz.hs b/src/VeriFuzz.hs index 4f52108..6c1a1b5 100644 --- a/src/VeriFuzz.hs +++ b/src/VeriFuzz.hs @@ -1,6 +1,6 @@ {-| -Module : VeriFuzz -Description : VeriFuzz +Module : VeriSmith +Description : VeriSmith Copyright : (c) 2018-2019, Yann Herklotz License : BSD-3 Maintainer : yann [at] yannherklotz [dot] com @@ -10,7 +10,7 @@ Portability : POSIX {-# OPTIONS_GHC -Wno-unused-top-binds #-} -module VeriFuzz +module VeriSmith ( defaultMain -- * Types , Opts(..) @@ -27,12 +27,12 @@ module VeriFuzz , proceduralSrcIO , randomMod -- * Extra modules - , module VeriFuzz.Verilog - , module VeriFuzz.Config - , module VeriFuzz.Circuit - , module VeriFuzz.Sim - , module VeriFuzz.Fuzz - , module VeriFuzz.Report + , module VeriSmith.Verilog + , module VeriSmith.Config + , module VeriSmith.Circuit + , module VeriSmith.Sim + , module VeriSmith.Fuzz + , module VeriSmith.Report ) where @@ -58,17 +58,17 @@ import Prelude hiding (FilePath) import Shelly hiding (command) import Shelly.Lifted (liftSh) import System.Random (randomIO) -import VeriFuzz.Circuit -import VeriFuzz.Config -import VeriFuzz.Fuzz -import VeriFuzz.Generate -import VeriFuzz.Reduce -import VeriFuzz.Report -import VeriFuzz.Result -import VeriFuzz.Sim -import VeriFuzz.Sim.Internal -import VeriFuzz.Verilog -import VeriFuzz.Verilog.Parser (parseSourceInfoFile) +import VeriSmith.Circuit +import VeriSmith.Config +import VeriSmith.Fuzz +import VeriSmith.Generate +import VeriSmith.Reduce +import VeriSmith.Report +import VeriSmith.Result +import VeriSmith.Sim +import VeriSmith.Sim.Internal +import VeriSmith.Verilog +import VeriSmith.Verilog.Parser (parseSourceInfoFile) data OptTool = TYosys | TXST @@ -315,7 +315,7 @@ opts = info ( fullDesc <> progDesc "Fuzz different simulators and synthesisers." <> header - "VeriFuzz - A hardware simulator and synthesiser Verilog fuzzer." + "VeriSmith - A hardware simulator and synthesiser Verilog fuzzer." ) getConfig :: Maybe FilePath -> IO Config @@ -504,7 +504,7 @@ checkEquivalence :: SourceInfo -> Text -> IO Bool checkEquivalence src dir = shellyFailDir $ do mkdir_p (fromText dir) curr <- toTextIgnore <$> pwd - setenv "VERIFUZZ_ROOT" curr + setenv "VERISMITH_ROOT" curr cd (fromText dir) catch_sh ((runResultT $ runEquiv defaultYosys defaultVivado src) >> return True) @@ -527,7 +527,7 @@ runEquivalence seed gm t d k i = do shellyFailDir $ do mkdir_p (fromText d </> fromText n) curr <- toTextIgnore <$> pwd - setenv "VERIFUZZ_ROOT" curr + setenv "VERISMITH_ROOT" curr cd (fromText "output" </> fromText n) _ <- catch_sh diff --git a/src/VeriFuzz/Circuit.hs b/src/VeriFuzz/Circuit.hs index 6083c8e..aee0d57 100644 --- a/src/VeriFuzz/Circuit.hs +++ b/src/VeriFuzz/Circuit.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Circuit +Module : VeriSmith.Circuit Description : Definition of the circuit graph. Copyright : (c) 2018-2019, Yann Herklotz License : BSD-3 @@ -10,7 +10,7 @@ Portability : POSIX Definition of the circuit graph. -} -module VeriFuzz.Circuit +module VeriSmith.Circuit ( -- * Circuit Gate(..) , Circuit(..) @@ -26,13 +26,13 @@ module VeriFuzz.Circuit where import Control.Lens -import Hedgehog (Gen) -import qualified Hedgehog.Gen as Hog -import VeriFuzz.Circuit.Base -import VeriFuzz.Circuit.Gen -import VeriFuzz.Circuit.Random -import VeriFuzz.Verilog.AST -import VeriFuzz.Verilog.Mutate +import Hedgehog (Gen) +import qualified Hedgehog.Gen as Hog +import VeriSmith.Circuit.Base +import VeriSmith.Circuit.Gen +import VeriSmith.Circuit.Random +import VeriSmith.Verilog.AST +import VeriSmith.Verilog.Mutate fromGraph :: Gen ModDecl fromGraph = do diff --git a/src/VeriFuzz/Circuit/Base.hs b/src/VeriFuzz/Circuit/Base.hs index 0bcdf39..ddcaf65 100644 --- a/src/VeriFuzz/Circuit/Base.hs +++ b/src/VeriFuzz/Circuit/Base.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Circuit.Base +Module : VeriSmith.Circuit.Base Description : Base types for the circuit module. Copyright : (c) 2019, Yann Herklotz Grave License : GPL-3 @@ -10,7 +10,7 @@ Portability : POSIX Base types for the circuit module. -} -module VeriFuzz.Circuit.Base +module VeriSmith.Circuit.Base ( Gate(..) , Circuit(..) , CNode(..) diff --git a/src/VeriFuzz/Circuit/Gen.hs b/src/VeriFuzz/Circuit/Gen.hs index eb7cb97..1c4dd37 100644 --- a/src/VeriFuzz/Circuit/Gen.hs +++ b/src/VeriFuzz/Circuit/Gen.hs @@ -10,18 +10,18 @@ Portability : POSIX Generate verilog from circuit. -} -module VeriFuzz.Circuit.Gen +module VeriSmith.Circuit.Gen ( generateAST ) where -import Data.Graph.Inductive (LNode, Node) -import qualified Data.Graph.Inductive as G -import Data.Maybe (catMaybes) -import VeriFuzz.Circuit.Base -import VeriFuzz.Circuit.Internal -import VeriFuzz.Verilog.AST -import VeriFuzz.Verilog.Mutate +import Data.Graph.Inductive (LNode, Node) +import qualified Data.Graph.Inductive as G +import Data.Maybe (catMaybes) +import VeriSmith.Circuit.Base +import VeriSmith.Circuit.Internal +import VeriSmith.Verilog.AST +import VeriSmith.Verilog.Mutate -- | Converts a 'CNode' to an 'Identifier'. frNode :: Node -> Identifier diff --git a/src/VeriFuzz/Circuit/Internal.hs b/src/VeriFuzz/Circuit/Internal.hs index 17e1586..b746738 100644 --- a/src/VeriFuzz/Circuit/Internal.hs +++ b/src/VeriFuzz/Circuit/Internal.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Circuit.Internal +Module : VeriSmith.Circuit.Internal Description : Internal helpers for generation. Copyright : (c) 2018-2019, Yann Herklotz License : BSD-3 @@ -10,7 +10,7 @@ Portability : POSIX Internal helpers for generation. -} -module VeriFuzz.Circuit.Internal +module VeriSmith.Circuit.Internal ( fromNode , filterGr , only diff --git a/src/VeriFuzz/Circuit/Random.hs b/src/VeriFuzz/Circuit/Random.hs index fdb5253..ca8cc26 100644 --- a/src/VeriFuzz/Circuit/Random.hs +++ b/src/VeriFuzz/Circuit/Random.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Circuit.Random +Module : VeriSmith.Circuit.Random Description : Random generation for DAG Copyright : (c) 2018-2019, Yann Herklotz License : BSD-3 @@ -10,7 +10,7 @@ Portability : POSIX Define the random generation for the directed acyclic graph. -} -module VeriFuzz.Circuit.Random +module VeriSmith.Circuit.Random ( rDups , rDupsCirc , randomDAG @@ -25,7 +25,7 @@ import Data.List (nub) import Hedgehog (Gen) import qualified Hedgehog.Gen as Hog import qualified Hedgehog.Range as Hog -import VeriFuzz.Circuit.Base +import VeriSmith.Circuit.Base dupFolder :: (Eq a, Eq b) => Context a b -> [Context a b] -> [Context a b] dupFolder cont ns = unique cont : ns diff --git a/src/VeriFuzz/Config.hs b/src/VeriFuzz/Config.hs index 8705f7c..adc3d19 100644 --- a/src/VeriFuzz/Config.hs +++ b/src/VeriFuzz/Config.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Config +Module : VeriSmith.Config Description : Configuration file format and parser. Copyright : (c) 2019, Yann Herklotz License : GPL-3 @@ -12,7 +12,7 @@ TOML Configuration file format and parser. {-# LANGUAGE TemplateHaskell #-} -module VeriFuzz.Config +module VeriSmith.Config ( -- * TOML Configuration -- $conf Config(..) @@ -88,18 +88,18 @@ import qualified Data.Text.IO as T import Data.Version (showVersion) import Development.GitRev import Hedgehog.Internal.Seed (Seed) -import Paths_verifuzz (version) +import Paths_verismith (version) import Shelly (toTextIgnore) import Toml (TomlCodec, (.=)) import qualified Toml -import VeriFuzz.Sim.Quartus -import VeriFuzz.Sim.Vivado -import VeriFuzz.Sim.XST -import VeriFuzz.Sim.Yosys +import VeriSmith.Sim.Quartus +import VeriSmith.Sim.Vivado +import VeriSmith.Sim.XST +import VeriSmith.Sim.Yosys -- $conf -- --- VeriFuzz supports a TOML configuration file that can be passed using the @-c@ +-- VeriSmith supports a TOML configuration file that can be passed using the @-c@ -- flag or using the 'parseConfig' and 'encodeConfig' functions. The -- configuration can then be manipulated using the lenses that are also provided -- in this module. @@ -111,7 +111,7 @@ import VeriFuzz.Sim.Yosys -- exact generation. A default value is associated with each key in the -- configuration file, which means that only the options that need overriding -- can be added to the configuration. The defaults can be observed in --- 'defaultConfig' or when running @verifuzz config@. +-- 'defaultConfig' or when running @verismith config@. -- -- == Configuration Sections -- @@ -487,7 +487,7 @@ encodeConfigFile f = T.writeFile f . encodeConfig versionInfo :: String versionInfo = - "VeriFuzz " + "VeriSmith " <> showVersion version <> " (" <> $(gitCommitDate) diff --git a/src/VeriFuzz/Fuzz.hs b/src/VeriFuzz/Fuzz.hs index df0ee2d..9331a5e 100644 --- a/src/VeriFuzz/Fuzz.hs +++ b/src/VeriFuzz/Fuzz.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Fuzz +Module : VeriSmith.Fuzz Description : Environment to run the simulator and synthesisers in a matrix. Copyright : (c) 2019, Yann Herklotz License : GPL-3 @@ -14,7 +14,7 @@ Environment to run the simulator and synthesisers in a matrix. {-# LANGUAGE FlexibleContexts #-} {-# LANGUAGE TemplateHaskell #-} -module VeriFuzz.Fuzz +module VeriSmith.Fuzz ( Fuzz , fuzz , fuzzInDir @@ -54,16 +54,16 @@ import Prelude hiding (FilePath) import Shelly hiding (get) import Shelly.Lifted (MonadSh, liftSh) import System.FilePath.Posix (takeBaseName) -import VeriFuzz.Config -import VeriFuzz.Internal -import VeriFuzz.Reduce -import VeriFuzz.Report -import VeriFuzz.Result -import VeriFuzz.Sim.Icarus -import VeriFuzz.Sim.Internal -import VeriFuzz.Sim.Yosys -import VeriFuzz.Verilog.AST -import VeriFuzz.Verilog.CodeGen +import VeriSmith.Config +import VeriSmith.Internal +import VeriSmith.Reduce +import VeriSmith.Report +import VeriSmith.Result +import VeriSmith.Sim.Icarus +import VeriSmith.Sim.Internal +import VeriSmith.Sim.Yosys +import VeriSmith.Verilog.AST +import VeriSmith.Verilog.CodeGen data FuzzEnv = FuzzEnv { getSynthesisers :: ![SynthTool] , getSimulators :: ![SimTool] diff --git a/src/VeriFuzz/Generate.hs b/src/VeriFuzz/Generate.hs index a82f56b..095baee 100644 --- a/src/VeriFuzz/Generate.hs +++ b/src/VeriFuzz/Generate.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Generate +Module : VeriSmith.Generate Description : Various useful generators. Copyright : (c) 2019, Yann Herklotz License : GPL-3 @@ -13,7 +13,7 @@ Various useful generators. {-# LANGUAGE TemplateHaskell #-} {-# OPTIONS_GHC -Wno-unused-imports #-} -module VeriFuzz.Generate +module VeriSmith.Generate ( -- * Generation methods procedural , proceduralIO @@ -73,13 +73,13 @@ import qualified Data.Text as T import Hedgehog (Gen) import qualified Hedgehog.Gen as Hog import qualified Hedgehog.Range as Hog -import VeriFuzz.Config -import VeriFuzz.Internal -import VeriFuzz.Verilog.AST -import VeriFuzz.Verilog.BitVec -import VeriFuzz.Verilog.Eval -import VeriFuzz.Verilog.Internal -import VeriFuzz.Verilog.Mutate +import VeriSmith.Config +import VeriSmith.Internal +import VeriSmith.Verilog.AST +import VeriSmith.Verilog.BitVec +import VeriSmith.Verilog.Eval +import VeriSmith.Verilog.Internal +import VeriSmith.Verilog.Mutate data Context = Context { _variables :: [Port] , _parameters :: [Parameter] diff --git a/src/VeriFuzz/Internal.hs b/src/VeriFuzz/Internal.hs index c7105fc..86cb1f7 100644 --- a/src/VeriFuzz/Internal.hs +++ b/src/VeriFuzz/Internal.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Internal +Module : VeriSmith.Internal Description : Shared high level code used in the other modules internally. Copyright : (c) 2018-2019, Yann Herklotz License : BSD-3 @@ -10,7 +10,7 @@ Portability : POSIX Shared high level code used in the other modules internally. -} -module VeriFuzz.Internal +module VeriSmith.Internal ( -- * Useful functions safe , showT diff --git a/src/VeriFuzz/Reduce.hs b/src/VeriFuzz/Reduce.hs index 61b7bba..c57b457 100644 --- a/src/VeriFuzz/Reduce.hs +++ b/src/VeriFuzz/Reduce.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Reduce +Module : VeriSmith.Reduce Description : Test case reducer implementation. Copyright : (c) 2019, Yann Herklotz License : GPL-3 @@ -13,7 +13,7 @@ Test case reducer implementation. {-# LANGUAGE RankNTypes #-} {-# LANGUAGE ScopedTypeVariables #-} -module VeriFuzz.Reduce +module VeriSmith.Reduce ( -- $strategy reduceWithScript , reduceSynth @@ -35,26 +35,26 @@ module VeriFuzz.Reduce ) where -import Control.Lens hiding ((<.>)) -import Control.Monad (void) -import Control.Monad.IO.Class (MonadIO, liftIO) -import Data.Foldable (foldrM) -import Data.List (nub) -import Data.List.NonEmpty (NonEmpty (..)) -import qualified Data.List.NonEmpty as NonEmpty -import Data.Maybe (mapMaybe) -import Data.Text (Text) -import Shelly ((<.>)) +import Control.Lens hiding ((<.>)) +import Control.Monad (void) +import Control.Monad.IO.Class (MonadIO, liftIO) +import Data.Foldable (foldrM) +import Data.List (nub) +import Data.List.NonEmpty (NonEmpty (..)) +import qualified Data.List.NonEmpty as NonEmpty +import Data.Maybe (mapMaybe) +import Data.Text (Text) +import Shelly ((<.>)) import qualified Shelly -import Shelly.Lifted (MonadSh, liftSh) -import VeriFuzz.Internal -import VeriFuzz.Result -import VeriFuzz.Sim -import VeriFuzz.Sim.Internal -import VeriFuzz.Verilog -import VeriFuzz.Verilog.AST -import VeriFuzz.Verilog.Mutate -import VeriFuzz.Verilog.Parser +import Shelly.Lifted (MonadSh, liftSh) +import VeriSmith.Internal +import VeriSmith.Result +import VeriSmith.Sim +import VeriSmith.Sim.Internal +import VeriSmith.Verilog +import VeriSmith.Verilog.AST +import VeriSmith.Verilog.Mutate +import VeriSmith.Verilog.Parser -- $strategy diff --git a/src/VeriFuzz/Report.hs b/src/VeriFuzz/Report.hs index 56fd062..fe680c3 100644 --- a/src/VeriFuzz/Report.hs +++ b/src/VeriFuzz/Report.hs @@ -1,6 +1,6 @@ {-# LANGUAGE RankNTypes #-} {-| -Module : VeriFuzz.Report +Module : VeriSmith.Report Description : Generate a report from a fuzz run. Copyright : (c) 2019, Yann Herklotz Grave License : GPL-3 @@ -13,7 +13,7 @@ Generate a report from a fuzz run. {-# LANGUAGE TemplateHaskell #-} -module VeriFuzz.Report +module VeriSmith.Report ( SynthTool(..) , SynthStatus(..) , SynthResult(..) @@ -60,11 +60,11 @@ import Text.Blaze.Html (Html, (!)) import Text.Blaze.Html.Renderer.Text (renderHtml) import qualified Text.Blaze.Html5 as H import qualified Text.Blaze.Html5.Attributes as A -import VeriFuzz.Config -import VeriFuzz.Internal -import VeriFuzz.Result -import VeriFuzz.Sim -import VeriFuzz.Sim.Internal +import VeriSmith.Config +import VeriSmith.Internal +import VeriSmith.Result +import VeriSmith.Sim +import VeriSmith.Sim.Internal -- | Common type alias for synthesis results type UResult = Result Failed () diff --git a/src/VeriFuzz/Result.hs b/src/VeriFuzz/Result.hs index 61b1452..7bfbf9b 100644 --- a/src/VeriFuzz/Result.hs +++ b/src/VeriFuzz/Result.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Result +Module : VeriSmith.Result Description : Result monadic type. Copyright : (c) 2019, Yann Herklotz Grave License : GPL-3 @@ -9,7 +9,7 @@ Portability : POSIX Result monadic type. This is nearly equivalent to the transformers 'Error' type, but to have more control this is reimplemented with the instances that are -needed in "VeriFuzz". +needed in "VeriSmith". -} {-# LANGUAGE FlexibleContexts #-} @@ -19,7 +19,7 @@ needed in "VeriFuzz". {-# LANGUAGE TypeFamilies #-} {-# LANGUAGE UndecidableInstances #-} -module VeriFuzz.Result +module VeriSmith.Result ( Result(..) , ResultT(..) , (<?>) diff --git a/src/VeriFuzz/Sim.hs b/src/VeriFuzz/Sim.hs index 92d1bc4..f0489d3 100644 --- a/src/VeriFuzz/Sim.hs +++ b/src/VeriFuzz/Sim.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Sim +Module : VeriSmith.Sim Description : Simulator implementations. Copyright : (c) 2019, Yann Herklotz Grave License : GPL-3 @@ -10,7 +10,7 @@ Portability : POSIX Simulator implementations. -} -module VeriFuzz.Sim +module VeriSmith.Sim ( -- * Simulators -- ** Icarus @@ -42,10 +42,10 @@ module VeriFuzz.Sim ) where -import VeriFuzz.Sim.Icarus -import VeriFuzz.Sim.Identity -import VeriFuzz.Sim.Internal -import VeriFuzz.Sim.Quartus -import VeriFuzz.Sim.Vivado -import VeriFuzz.Sim.XST -import VeriFuzz.Sim.Yosys +import VeriSmith.Sim.Icarus +import VeriSmith.Sim.Identity +import VeriSmith.Sim.Internal +import VeriSmith.Sim.Quartus +import VeriSmith.Sim.Vivado +import VeriSmith.Sim.XST +import VeriSmith.Sim.Yosys diff --git a/src/VeriFuzz/Sim/Icarus.hs b/src/VeriFuzz/Sim/Icarus.hs index e7c92dc..f104630 100644 --- a/src/VeriFuzz/Sim/Icarus.hs +++ b/src/VeriFuzz/Sim/Icarus.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Sim.Icarus +Module : VeriSmith.Sim.Icarus Description : Icarus verilog module. Copyright : (c) 2018-2019, Yann Herklotz License : BSD-3 @@ -10,42 +10,42 @@ Portability : POSIX Icarus verilog module. -} -module VeriFuzz.Sim.Icarus +module VeriSmith.Sim.Icarus ( Icarus(..) , defaultIcarus , runSimIc ) where -import Control.DeepSeq (NFData, rnf, rwhnf) +import Control.DeepSeq (NFData, rnf, rwhnf) import Control.Lens -import Control.Monad (void) -import Crypto.Hash (Digest, hash) -import Crypto.Hash.Algorithms (SHA256) -import Data.Binary (encode) +import Control.Monad (void) +import Crypto.Hash (Digest, hash) +import Crypto.Hash.Algorithms (SHA256) +import Data.Binary (encode) import Data.Bits -import qualified Data.ByteArray as BA (convert) -import Data.ByteString (ByteString) -import qualified Data.ByteString as B -import Data.ByteString.Lazy (toStrict) -import qualified Data.ByteString.Lazy as L (ByteString) -import Data.Char (digitToInt) -import Data.Foldable (fold) -import Data.List (transpose) -import Data.Maybe (listToMaybe) -import Data.Text (Text) -import qualified Data.Text as T -import Numeric (readInt) -import Prelude hiding (FilePath) +import qualified Data.ByteArray as BA (convert) +import Data.ByteString (ByteString) +import qualified Data.ByteString as B +import Data.ByteString.Lazy (toStrict) +import qualified Data.ByteString.Lazy as L (ByteString) +import Data.Char (digitToInt) +import Data.Foldable (fold) +import Data.List (transpose) +import Data.Maybe (listToMaybe) +import Data.Text (Text) +import qualified Data.Text as T +import Numeric (readInt) +import Prelude hiding (FilePath) import Shelly -import Shelly.Lifted (liftSh) -import VeriFuzz.Sim.Internal -import VeriFuzz.Sim.Template -import VeriFuzz.Verilog.AST -import VeriFuzz.Verilog.BitVec -import VeriFuzz.Verilog.CodeGen -import VeriFuzz.Verilog.Internal -import VeriFuzz.Verilog.Mutate +import Shelly.Lifted (liftSh) +import VeriSmith.Sim.Internal +import VeriSmith.Sim.Template +import VeriSmith.Verilog.AST +import VeriSmith.Verilog.BitVec +import VeriSmith.Verilog.CodeGen +import VeriSmith.Verilog.Internal +import VeriSmith.Verilog.Mutate data Icarus = Icarus { icarusPath :: FilePath , vvpPath :: FilePath diff --git a/src/VeriFuzz/Sim/Identity.hs b/src/VeriFuzz/Sim/Identity.hs index bfa99f5..cac230f 100644 --- a/src/VeriFuzz/Sim/Identity.hs +++ b/src/VeriFuzz/Sim/Identity.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Sim.Identity +Module : VeriSmith.Sim.Identity Description : The identity simulator and synthesiser. Copyright : (c) 2019, Yann Herklotz Grave License : GPL-3 @@ -10,20 +10,20 @@ Portability : POSIX The identity simulator and synthesiser. -} -module VeriFuzz.Sim.Identity +module VeriSmith.Sim.Identity ( Identity(..) , defaultIdentity ) where -import Control.DeepSeq (NFData, rnf, rwhnf) -import Data.Text (Text, unpack) -import Prelude hiding (FilePath) -import Shelly (FilePath) -import Shelly.Lifted (writefile) -import VeriFuzz.Sim.Internal -import VeriFuzz.Verilog.AST -import VeriFuzz.Verilog.CodeGen +import Control.DeepSeq (NFData, rnf, rwhnf) +import Data.Text (Text, unpack) +import Prelude hiding (FilePath) +import Shelly (FilePath) +import Shelly.Lifted (writefile) +import VeriSmith.Sim.Internal +import VeriSmith.Verilog.AST +import VeriSmith.Verilog.CodeGen data Identity = Identity { identityDesc :: {-# UNPACK #-} !Text , identityOutput :: {-# UNPACK #-} !FilePath diff --git a/src/VeriFuzz/Sim/Internal.hs b/src/VeriFuzz/Sim/Internal.hs index f5351c7..017faad 100644 --- a/src/VeriFuzz/Sim/Internal.hs +++ b/src/VeriFuzz/Sim/Internal.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Sim.Internal +Module : VeriSmith.Sim.Internal Description : Class of the simulator. Copyright : (c) 2018-2019, Yann Herklotz License : BSD-3 @@ -12,7 +12,7 @@ Class of the simulator and the synthesize tool. {-# LANGUAGE DeriveFunctor #-} -module VeriFuzz.Sim.Internal +module VeriSmith.Sim.Internal ( ResultSh , resultSh , Tool(..) @@ -54,9 +54,9 @@ import Prelude hiding (FilePath) import Shelly import Shelly.Lifted (MonadSh, liftSh) import System.FilePath.Posix (takeBaseName) -import VeriFuzz.Internal -import VeriFuzz.Result -import VeriFuzz.Verilog.AST +import VeriSmith.Internal +import VeriSmith.Result +import VeriSmith.Verilog.AST -- | Tool class. class Tool a where @@ -100,7 +100,7 @@ renameSource :: (Synthesiser a) => a -> SourceInfo -> SourceInfo renameSource a src = src & infoSrc . _Wrapped . traverse . modId . _Wrapped %~ (<> toText a) --- | Type synonym for a 'ResultT' that will be used throughout 'VeriFuzz'. This +-- | Type synonym for a 'ResultT' that will be used throughout 'VeriSmith'. This -- has instances for 'MonadSh' and 'MonadIO' if the 'Monad' it is parametrised -- with also has those instances. type ResultSh = ResultT Failed Sh @@ -146,7 +146,7 @@ replaceMods fp t (SourceInfo _ src) = rootPath :: Sh FilePath rootPath = do current <- pwd - maybe current fromText <$> get_env "VERIFUZZ_ROOT" + maybe current fromText <$> get_env "VERISMITH_ROOT" timeout :: FilePath -> [Text] -> Sh Text timeout = command1 "timeout" ["300"] . toTextIgnore @@ -170,7 +170,7 @@ logger t = do fn <- pwd currentTime <- liftIO getZonedTime echo - $ "VeriFuzz " + $ "VeriSmith " <> T.pack (formatTime defaultTimeLocale "%H:%M:%S " currentTime) <> bname fn <> " - " diff --git a/src/VeriFuzz/Sim/Quartus.hs b/src/VeriFuzz/Sim/Quartus.hs index 254bfa5..6837133 100644 --- a/src/VeriFuzz/Sim/Quartus.hs +++ b/src/VeriFuzz/Sim/Quartus.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Sim.Quartus +Module : VeriSmith.Sim.Quartus Description : Quartus synthesiser implementation. Copyright : (c) 2019, Yann Herklotz Grave License : GPL-3 @@ -10,20 +10,20 @@ Portability : POSIX Quartus synthesiser implementation. -} -module VeriFuzz.Sim.Quartus +module VeriSmith.Sim.Quartus ( Quartus(..) , defaultQuartus ) where -import Control.DeepSeq (NFData, rnf, rwhnf) -import Data.Text (Text, unpack) -import Prelude hiding (FilePath) +import Control.DeepSeq (NFData, rnf, rwhnf) +import Data.Text (Text, unpack) +import Prelude hiding (FilePath) import Shelly -import Shelly.Lifted (liftSh) -import VeriFuzz.Sim.Internal -import VeriFuzz.Verilog.AST -import VeriFuzz.Verilog.CodeGen +import Shelly.Lifted (liftSh) +import VeriSmith.Sim.Internal +import VeriSmith.Verilog.AST +import VeriSmith.Verilog.CodeGen data Quartus = Quartus { quartusBin :: !(Maybe FilePath) , quartusDesc :: {-# UNPACK #-} !Text diff --git a/src/VeriFuzz/Sim/Template.hs b/src/VeriFuzz/Sim/Template.hs index 9b8ee9f..d232420 100644 --- a/src/VeriFuzz/Sim/Template.hs +++ b/src/VeriFuzz/Sim/Template.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Sim.Template +Module : VeriSmith.Sim.Template Description : Template file for different configuration files Copyright : (c) 2019, Yann Herklotz License : GPL-3 @@ -12,7 +12,7 @@ Template file for different configuration files. {-# LANGUAGE QuasiQuotes #-} -module VeriFuzz.Sim.Template +module VeriSmith.Sim.Template ( yosysSatConfig , yosysSimConfig , xstSynthConfig @@ -22,15 +22,15 @@ module VeriFuzz.Sim.Template ) where -import Control.Lens ((^..)) -import Data.Text (Text) -import qualified Data.Text as T -import Prelude hiding (FilePath) +import Control.Lens ((^..)) +import Data.Text (Text) +import qualified Data.Text as T +import Prelude hiding (FilePath) import Shelly -import Text.Shakespeare.Text (st) -import VeriFuzz.Sim.Internal -import VeriFuzz.Verilog.AST -import VeriFuzz.Verilog.CodeGen +import Text.Shakespeare.Text (st) +import VeriSmith.Sim.Internal +import VeriSmith.Verilog.AST +import VeriSmith.Verilog.CodeGen rename :: Text -> [Text] -> Text rename end entries = diff --git a/src/VeriFuzz/Sim/Vivado.hs b/src/VeriFuzz/Sim/Vivado.hs index 4ddb048..e8d8f0d 100644 --- a/src/VeriFuzz/Sim/Vivado.hs +++ b/src/VeriFuzz/Sim/Vivado.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Sim.Vivado +Module : VeriSmith.Sim.Vivado Description : Vivado Synthesiser implementation. Copyright : (c) 2019, Yann Herklotz Grave License : GPL-3 @@ -10,21 +10,21 @@ Portability : POSIX Vivado Synthesiser implementation. -} -module VeriFuzz.Sim.Vivado +module VeriSmith.Sim.Vivado ( Vivado(..) , defaultVivado ) where -import Control.DeepSeq (NFData, rnf, rwhnf) -import Data.Text (Text, unpack) -import Prelude hiding (FilePath) +import Control.DeepSeq (NFData, rnf, rwhnf) +import Data.Text (Text, unpack) +import Prelude hiding (FilePath) import Shelly -import Shelly.Lifted (liftSh) -import VeriFuzz.Sim.Internal -import VeriFuzz.Sim.Template -import VeriFuzz.Verilog.AST -import VeriFuzz.Verilog.CodeGen +import Shelly.Lifted (liftSh) +import VeriSmith.Sim.Internal +import VeriSmith.Sim.Template +import VeriSmith.Verilog.AST +import VeriSmith.Verilog.CodeGen data Vivado = Vivado { vivadoBin :: !(Maybe FilePath) , vivadoDesc :: {-# UNPACK #-} !Text diff --git a/src/VeriFuzz/Sim/XST.hs b/src/VeriFuzz/Sim/XST.hs index 86db667..30a4b0b 100644 --- a/src/VeriFuzz/Sim/XST.hs +++ b/src/VeriFuzz/Sim/XST.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Sim.XST +Module : VeriSmith.Sim.XST Description : XST (ise) simulator implementation. Copyright : (c) 2018-2019, Yann Herklotz License : BSD-3 @@ -12,22 +12,22 @@ XST (ise) simulator implementation. {-# LANGUAGE QuasiQuotes #-} -module VeriFuzz.Sim.XST +module VeriSmith.Sim.XST ( XST(..) , defaultXST ) where -import Control.DeepSeq (NFData, rnf, rwhnf) -import Data.Text (Text, unpack) -import Prelude hiding (FilePath) +import Control.DeepSeq (NFData, rnf, rwhnf) +import Data.Text (Text, unpack) +import Prelude hiding (FilePath) import Shelly -import Shelly.Lifted (liftSh) -import Text.Shakespeare.Text (st) -import VeriFuzz.Sim.Internal -import VeriFuzz.Sim.Template -import VeriFuzz.Verilog.AST -import VeriFuzz.Verilog.CodeGen +import Shelly.Lifted (liftSh) +import Text.Shakespeare.Text (st) +import VeriSmith.Sim.Internal +import VeriSmith.Sim.Template +import VeriSmith.Verilog.AST +import VeriSmith.Verilog.CodeGen data XST = XST { xstBin :: !(Maybe FilePath) , xstDesc :: {-# UNPACK #-} !Text diff --git a/src/VeriFuzz/Sim/Yosys.hs b/src/VeriFuzz/Sim/Yosys.hs index 8c73b86..1f583a8 100644 --- a/src/VeriFuzz/Sim/Yosys.hs +++ b/src/VeriFuzz/Sim/Yosys.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Sim.Yosys +Module : VeriSmith.Sim.Yosys Description : Yosys simulator implementation. Copyright : (c) 2018-2019, Yann Herklotz License : BSD-3 @@ -12,7 +12,7 @@ Yosys simulator implementation. {-# LANGUAGE QuasiQuotes #-} -module VeriFuzz.Sim.Yosys +module VeriSmith.Sim.Yosys ( Yosys(..) , defaultYosys , runEquiv @@ -20,20 +20,20 @@ module VeriFuzz.Sim.Yosys ) where -import Control.DeepSeq (NFData, rnf, rwhnf) +import Control.DeepSeq (NFData, rnf, rwhnf) import Control.Lens -import Control.Monad (void) -import Data.Text (Text, unpack) -import Prelude hiding (FilePath) +import Control.Monad (void) +import Data.Text (Text, unpack) +import Prelude hiding (FilePath) import Shelly -import Shelly.Lifted (liftSh) -import Text.Shakespeare.Text (st) -import VeriFuzz.Result -import VeriFuzz.Sim.Internal -import VeriFuzz.Sim.Template -import VeriFuzz.Verilog.AST -import VeriFuzz.Verilog.CodeGen -import VeriFuzz.Verilog.Mutate +import Shelly.Lifted (liftSh) +import Text.Shakespeare.Text (st) +import VeriSmith.Result +import VeriSmith.Sim.Internal +import VeriSmith.Sim.Template +import VeriSmith.Verilog.AST +import VeriSmith.Verilog.CodeGen +import VeriSmith.Verilog.Mutate data Yosys = Yosys { yosysBin :: !(Maybe FilePath) , yosysDesc :: {-# UNPACK #-} !Text diff --git a/src/VeriFuzz/Verilog.hs b/src/VeriFuzz/Verilog.hs index 4b5029c..6e7851c 100644 --- a/src/VeriFuzz/Verilog.hs +++ b/src/VeriFuzz/Verilog.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Verilog +Module : VeriSmith.Verilog Description : Verilog implementation with random generation and mutations. Copyright : (c) 2019, Yann Herklotz Grave License : GPL-3 @@ -12,7 +12,7 @@ Verilog implementation with random generation and mutations. {-# LANGUAGE QuasiQuotes #-} -module VeriFuzz.Verilog +module VeriSmith.Verilog ( SourceInfo(..) , Verilog(..) , parseVerilog @@ -100,7 +100,7 @@ module VeriFuzz.Verilog ) where -import VeriFuzz.Verilog.AST -import VeriFuzz.Verilog.CodeGen -import VeriFuzz.Verilog.Parser -import VeriFuzz.Verilog.Quote +import VeriSmith.Verilog.AST +import VeriSmith.Verilog.CodeGen +import VeriSmith.Verilog.Parser +import VeriSmith.Verilog.Quote diff --git a/src/VeriFuzz/Verilog/AST.hs b/src/VeriFuzz/Verilog/AST.hs index a85c365..78bad45 100644 --- a/src/VeriFuzz/Verilog/AST.hs +++ b/src/VeriFuzz/Verilog/AST.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Verilog.AST +Module : VeriSmith.Verilog.AST Description : Definition of the Verilog AST types. Copyright : (c) 2018-2019, Yann Herklotz License : BSD-3 @@ -22,7 +22,7 @@ Defines the types to build a Verilog AST. {-# LANGUAGE TemplateHaskell #-} {-# LANGUAGE TypeFamilies #-} -module VeriFuzz.Verilog.AST +module VeriSmith.Verilog.AST ( -- * Top level types SourceInfo(..) , infoTop @@ -150,7 +150,7 @@ import Data.String (IsString, fromString) import Data.Text (Text, pack) import Data.Traversable (sequenceA) import GHC.Generics (Generic) -import VeriFuzz.Verilog.BitVec +import VeriSmith.Verilog.BitVec -- | Identifier in Verilog. This is just a string of characters that can either -- be lowercase and uppercase for now. This might change in the future though, diff --git a/src/VeriFuzz/Verilog/BitVec.hs b/src/VeriFuzz/Verilog/BitVec.hs index 0cc9eb3..dab9e2c 100644 --- a/src/VeriFuzz/Verilog/BitVec.hs +++ b/src/VeriFuzz/Verilog/BitVec.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Verilog.BitVec +Module : VeriSmith.Verilog.BitVec Description : Unsigned BitVec implementation. Copyright : (c) 2019, Yann Herklotz Grave License : GPL-3 @@ -17,7 +17,7 @@ Unsigned BitVec implementation. {-# LANGUAGE DeriveGeneric #-} {-# LANGUAGE DeriveTraversable #-} -module VeriFuzz.Verilog.BitVec +module VeriSmith.Verilog.BitVec ( BitVecF(..) , BitVec , bitVec diff --git a/src/VeriFuzz/Verilog/CodeGen.hs b/src/VeriFuzz/Verilog/CodeGen.hs index 56e2819..1e94472 100644 --- a/src/VeriFuzz/Verilog/CodeGen.hs +++ b/src/VeriFuzz/Verilog/CodeGen.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Verilog.CodeGen +Module : VeriSmith.Verilog.CodeGen Description : Code generation for Verilog AST. Copyright : (c) 2018-2019, Yann Herklotz License : BSD-3 @@ -8,13 +8,13 @@ Stability : experimental Portability : POSIX This module generates the code from the Verilog AST defined in -"VeriFuzz.Verilog.AST". +"VeriSmith.Verilog.AST". -} {-# LANGUAGE DeriveDataTypeable #-} {-# LANGUAGE FlexibleInstances #-} -module VeriFuzz.Verilog.CodeGen +module VeriSmith.Verilog.CodeGen ( -- * Code Generation GenVerilog(..) , Source(..) @@ -28,9 +28,9 @@ import Data.Text (Text) import qualified Data.Text as T import Data.Text.Prettyprint.Doc import Numeric (showHex) -import VeriFuzz.Internal hiding (comma) -import VeriFuzz.Verilog.AST -import VeriFuzz.Verilog.BitVec +import VeriSmith.Internal hiding (comma) +import VeriSmith.Verilog.AST +import VeriSmith.Verilog.BitVec -- | 'Source' class which determines that source code is able to be generated -- from the data structure using 'genSource'. This will be stored in 'Text' and diff --git a/src/VeriFuzz/Verilog/Eval.hs b/src/VeriFuzz/Verilog/Eval.hs index c802267..1ebaa80 100644 --- a/src/VeriFuzz/Verilog/Eval.hs +++ b/src/VeriFuzz/Verilog/Eval.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Verilog.Eval +Module : VeriSmith.Verilog.Eval Description : Evaluation of Verilog expressions and statements. Copyright : (c) 2019, Yann Herklotz Grave License : GPL-3 @@ -10,18 +10,18 @@ Portability : POSIX Evaluation of Verilog expressions and statements. -} -module VeriFuzz.Verilog.Eval +module VeriSmith.Verilog.Eval ( evaluateConst , resize ) where import Data.Bits -import Data.Foldable (fold) -import Data.Functor.Foldable hiding (fold) -import Data.Maybe (listToMaybe) -import VeriFuzz.Verilog.AST -import VeriFuzz.Verilog.BitVec +import Data.Foldable (fold) +import Data.Functor.Foldable hiding (fold) +import Data.Maybe (listToMaybe) +import VeriSmith.Verilog.AST +import VeriSmith.Verilog.BitVec type Bindings = [Parameter] diff --git a/src/VeriFuzz/Verilog/Internal.hs b/src/VeriFuzz/Verilog/Internal.hs index 42eb4e2..ed91b12 100644 --- a/src/VeriFuzz/Verilog/Internal.hs +++ b/src/VeriFuzz/Verilog/Internal.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Verilog.Internal +Module : VeriSmith.Verilog.Internal Description : Defaults and common functions. Copyright : (c) 2018-2019, Yann Herklotz License : BSD-3 @@ -10,7 +10,7 @@ Portability : POSIX Defaults and common functions. -} -module VeriFuzz.Verilog.Internal +module VeriSmith.Verilog.Internal ( regDecl , wireDecl , emptyMod @@ -29,8 +29,8 @@ module VeriFuzz.Verilog.Internal where import Control.Lens -import Data.Text (Text) -import VeriFuzz.Verilog.AST +import Data.Text (Text) +import VeriSmith.Verilog.AST regDecl :: Identifier -> ModItem regDecl i = Decl Nothing (Port Reg False (Range 1 0) i) Nothing diff --git a/src/VeriFuzz/Verilog/Lex.x b/src/VeriFuzz/Verilog/Lex.x index cc67ecc..3d1dd8d 100644 --- a/src/VeriFuzz/Verilog/Lex.x +++ b/src/VeriFuzz/Verilog/Lex.x @@ -1,11 +1,11 @@ -- -*- haskell -*- { {-# OPTIONS_GHC -w #-} -module VeriFuzz.Verilog.Lex +module VeriSmith.Verilog.Lex ( alexScanTokens ) where -import VeriFuzz.Verilog.Token +import VeriSmith.Verilog.Token } diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs index 37d3a7d..58675e3 100644 --- a/src/VeriFuzz/Verilog/Mutate.hs +++ b/src/VeriFuzz/Verilog/Mutate.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Verilog.Mutate +Module : VeriSmith.Verilog.Mutate Description : Functions to mutate the Verilog AST. Copyright : (c) 2018-2019, Yann Herklotz License : BSD-3 @@ -7,13 +7,13 @@ Maintainer : yann [at] yannherklotz [dot] com Stability : experimental Portability : POSIX -Functions to mutate the Verilog AST from "VeriFuzz.Verilog.AST" to generate more +Functions to mutate the Verilog AST from "VeriSmith.Verilog.AST" to generate more random patterns, such as nesting wires instead of creating new ones. -} {-# LANGUAGE FlexibleInstances #-} -module VeriFuzz.Verilog.Mutate +module VeriSmith.Verilog.Mutate ( Mutate(..) , inPort , findAssign @@ -41,16 +41,16 @@ module VeriFuzz.Verilog.Mutate where import Control.Lens -import Data.Foldable (fold) -import Data.Maybe (catMaybes, fromMaybe) -import Data.Text (Text) -import qualified Data.Text as T -import VeriFuzz.Circuit.Internal -import VeriFuzz.Internal -import VeriFuzz.Verilog.AST -import VeriFuzz.Verilog.BitVec -import VeriFuzz.Verilog.CodeGen -import VeriFuzz.Verilog.Internal +import Data.Foldable (fold) +import Data.Maybe (catMaybes, fromMaybe) +import Data.Text (Text) +import qualified Data.Text as T +import VeriSmith.Circuit.Internal +import VeriSmith.Internal +import VeriSmith.Verilog.AST +import VeriSmith.Verilog.BitVec +import VeriSmith.Verilog.CodeGen +import VeriSmith.Verilog.Internal class Mutate a where mutExpr :: (Expr -> Expr) -> a -> a @@ -210,7 +210,7 @@ allVars m = <> (m ^.. modInPorts . traverse . portName) -- $setup --- >>> import VeriFuzz.Verilog.CodeGen +-- >>> import VeriSmith.Verilog.CodeGen -- >>> let m = (ModDecl (Identifier "m") [Port Wire False 5 (Identifier "y")] [Port Wire False 5 "x"] [] []) -- >>> let main = (ModDecl "main" [] [] [] []) diff --git a/src/VeriFuzz/Verilog/Parser.hs b/src/VeriFuzz/Verilog/Parser.hs index c08ebcd..8d2b729 100644 --- a/src/VeriFuzz/Verilog/Parser.hs +++ b/src/VeriFuzz/Verilog/Parser.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Verilog.Parser +Module : VeriSmith.Verilog.Parser Description : Minimal Verilog parser to reconstruct the AST. Copyright : (c) 2019, Yann Herklotz License : GPL-3 @@ -11,7 +11,7 @@ Minimal Verilog parser to reconstruct the AST. This parser does not support the whole Verilog syntax, as the AST does not support it either. -} -module VeriFuzz.Verilog.Parser +module VeriSmith.Verilog.Parser ( -- * Parser parseVerilog , parseVerilogFile @@ -26,25 +26,25 @@ module VeriFuzz.Verilog.Parser where import Control.Lens -import Control.Monad (void) -import Data.Bifunctor (bimap) +import Control.Monad (void) +import Data.Bifunctor (bimap) import Data.Bits -import Data.Functor (($>)) -import Data.Functor.Identity (Identity) -import Data.List (isInfixOf, isPrefixOf, null) -import Data.List.NonEmpty (NonEmpty (..)) -import Data.Text (Text) -import qualified Data.Text as T -import qualified Data.Text.IO as T -import Text.Parsec hiding (satisfy) +import Data.Functor (($>)) +import Data.Functor.Identity (Identity) +import Data.List (isInfixOf, isPrefixOf, null) +import Data.List.NonEmpty (NonEmpty (..)) +import Data.Text (Text) +import qualified Data.Text as T +import qualified Data.Text.IO as T +import Text.Parsec hiding (satisfy) import Text.Parsec.Expr -import VeriFuzz.Internal -import VeriFuzz.Verilog.AST -import VeriFuzz.Verilog.BitVec -import VeriFuzz.Verilog.Internal -import VeriFuzz.Verilog.Lex -import VeriFuzz.Verilog.Preprocess -import VeriFuzz.Verilog.Token +import VeriSmith.Internal +import VeriSmith.Verilog.AST +import VeriSmith.Verilog.BitVec +import VeriSmith.Verilog.Internal +import VeriSmith.Verilog.Lex +import VeriSmith.Verilog.Preprocess +import VeriSmith.Verilog.Token type Parser = Parsec [Token] () diff --git a/src/VeriFuzz/Verilog/Preprocess.hs b/src/VeriFuzz/Verilog/Preprocess.hs index c783ac5..c30252b 100644 --- a/src/VeriFuzz/Verilog/Preprocess.hs +++ b/src/VeriFuzz/Verilog/Preprocess.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Verilog.Preprocess +Module : VeriSmith.Verilog.Preprocess Description : Simple preprocessor for `define and comments. Copyright : (c) 2011-2015 Tom Hawkins, 2019 Yann Herklotz License : GPL-3 @@ -14,7 +14,7 @@ The code is from https://github.com/tomahawkins/verilog. Edits to the original code are warning fixes and formatting changes. -} -module VeriFuzz.Verilog.Preprocess +module VeriSmith.Verilog.Preprocess ( uncomment , preprocess ) diff --git a/src/VeriFuzz/Verilog/Quote.hs b/src/VeriFuzz/Verilog/Quote.hs index c6d3e3c..3815fe6 100644 --- a/src/VeriFuzz/Verilog/Quote.hs +++ b/src/VeriFuzz/Verilog/Quote.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Verilog.Quote +Module : VeriSmith.Verilog.Quote Description : QuasiQuotation for verilog code in Haskell. Copyright : (c) 2019, Yann Herklotz Grave License : GPL-3 @@ -12,7 +12,7 @@ QuasiQuotation for verilog code in Haskell. {-# LANGUAGE TemplateHaskell #-} -module VeriFuzz.Verilog.Quote +module VeriSmith.Verilog.Quote ( verilog ) where @@ -22,7 +22,7 @@ import qualified Data.Text as T import qualified Language.Haskell.TH as TH import Language.Haskell.TH.Quote import Language.Haskell.TH.Syntax -import VeriFuzz.Verilog.Parser +import VeriSmith.Verilog.Parser liftDataWithText :: Data a => a -> Q Exp liftDataWithText = dataToExpQ $ fmap liftText . cast diff --git a/src/VeriFuzz/Verilog/Token.hs b/src/VeriFuzz/Verilog/Token.hs index d69f0b3..590672e 100644 --- a/src/VeriFuzz/Verilog/Token.hs +++ b/src/VeriFuzz/Verilog/Token.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Verilog.Token +Module : VeriSmith.Verilog.Token Description : Tokens for Verilog parsing. Copyright : (c) 2019, Yann Herklotz Grave License : GPL-3 @@ -10,7 +10,7 @@ Portability : POSIX Tokens for Verilog parsing. -} -module VeriFuzz.Verilog.Token +module VeriSmith.Verilog.Token ( Token(..) , TokenName(..) , Position(..) |