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-rw-r--r--src/Test/VeriFuzz/VerilogAST.hs5
1 files changed, 2 insertions, 3 deletions
diff --git a/src/Test/VeriFuzz/VerilogAST.hs b/src/Test/VeriFuzz/VerilogAST.hs
index d4514cc..8314acb 100644
--- a/src/Test/VeriFuzz/VerilogAST.hs
+++ b/src/Test/VeriFuzz/VerilogAST.hs
@@ -65,7 +65,7 @@ data Port = Port { _portName :: Identifier
} deriving (Show)
makeLenses ''Port
-newtype ModuleItem = ModuleItem { _getModuleItem :: Text }
+data ModuleItem = Assign ContAssign
deriving (Show)
makeLenses ''ModuleItem
@@ -81,6 +81,5 @@ newtype Description = Description { _getDescription :: ModuleDecl }
makeLenses ''Description
newtype SourceText = SourceText { _getSourceText :: [Description] }
- deriving (Show
- )
+ deriving (Show)
makeLenses ''SourceText