diff options
Diffstat (limited to 'src')
-rw-r--r-- | src/Verismith.hs (renamed from src/VeriSmith.hs) | 42 | ||||
-rw-r--r-- | src/Verismith/Circuit.hs (renamed from src/VeriSmith/Circuit.hs) | 14 | ||||
-rw-r--r-- | src/Verismith/Circuit/Base.hs (renamed from src/VeriSmith/Circuit/Base.hs) | 4 | ||||
-rw-r--r-- | src/Verismith/Circuit/Gen.hs (renamed from src/VeriSmith/Circuit/Gen.hs) | 10 | ||||
-rw-r--r-- | src/Verismith/Circuit/Internal.hs (renamed from src/VeriSmith/Circuit/Internal.hs) | 4 | ||||
-rw-r--r-- | src/Verismith/Circuit/Random.hs (renamed from src/VeriSmith/Circuit/Random.hs) | 6 | ||||
-rw-r--r-- | src/Verismith/Config.hs (renamed from src/VeriSmith/Config.hs) | 16 | ||||
-rw-r--r-- | src/Verismith/Fuzz.hs (renamed from src/VeriSmith/Fuzz.hs) | 24 | ||||
-rw-r--r-- | src/Verismith/Generate.hs (renamed from src/VeriSmith/Generate.hs) | 18 | ||||
-rw-r--r-- | src/Verismith/Internal.hs (renamed from src/VeriSmith/Internal.hs) | 4 | ||||
-rw-r--r-- | src/Verismith/Reduce.hs (renamed from src/VeriSmith/Reduce.hs) | 20 | ||||
-rw-r--r-- | src/Verismith/Report.hs (renamed from src/VeriSmith/Report.hs) | 14 | ||||
-rw-r--r-- | src/Verismith/Result.hs (renamed from src/VeriSmith/Result.hs) | 6 | ||||
-rw-r--r-- | src/Verismith/Sim.hs (renamed from src/VeriSmith/Sim.hs) | 18 | ||||
-rw-r--r-- | src/Verismith/Sim/Icarus.hs (renamed from src/VeriSmith/Sim/Icarus.hs) | 18 | ||||
-rw-r--r-- | src/Verismith/Sim/Identity.hs (renamed from src/VeriSmith/Sim/Identity.hs) | 10 | ||||
-rw-r--r-- | src/Verismith/Sim/Internal.hs (renamed from src/VeriSmith/Sim/Internal.hs) | 14 | ||||
-rw-r--r-- | src/Verismith/Sim/Quartus.hs (renamed from src/VeriSmith/Sim/Quartus.hs) | 10 | ||||
-rw-r--r-- | src/Verismith/Sim/Template.hs (renamed from src/VeriSmith/Sim/Template.hs) | 10 | ||||
-rw-r--r-- | src/Verismith/Sim/Vivado.hs (renamed from src/VeriSmith/Sim/Vivado.hs) | 12 | ||||
-rw-r--r-- | src/Verismith/Sim/XST.hs (renamed from src/VeriSmith/Sim/XST.hs) | 12 | ||||
-rw-r--r-- | src/Verismith/Sim/Yosys.hs (renamed from src/VeriSmith/Sim/Yosys.hs) | 16 | ||||
-rw-r--r-- | src/Verismith/Verilog.hs (renamed from src/VeriSmith/Verilog.hs) | 12 | ||||
-rw-r--r-- | src/Verismith/Verilog/AST.hs (renamed from src/VeriSmith/Verilog/AST.hs) | 6 | ||||
-rw-r--r-- | src/Verismith/Verilog/BitVec.hs (renamed from src/VeriSmith/Verilog/BitVec.hs) | 4 | ||||
-rw-r--r-- | src/Verismith/Verilog/CodeGen.hs (renamed from src/VeriSmith/Verilog/CodeGen.hs) | 12 | ||||
-rw-r--r-- | src/Verismith/Verilog/Eval.hs (renamed from src/VeriSmith/Verilog/Eval.hs) | 8 | ||||
-rw-r--r-- | src/Verismith/Verilog/Internal.hs (renamed from src/VeriSmith/Verilog/Internal.hs) | 6 | ||||
-rw-r--r-- | src/Verismith/Verilog/Lex.x (renamed from src/VeriSmith/Verilog/Lex.x) | 4 | ||||
-rw-r--r-- | src/Verismith/Verilog/Mutate.hs (renamed from src/VeriSmith/Verilog/Mutate.hs) | 20 | ||||
-rw-r--r-- | src/Verismith/Verilog/Parser.hs (renamed from src/VeriSmith/Verilog/Parser.hs) | 18 | ||||
-rw-r--r-- | src/Verismith/Verilog/Preprocess.hs (renamed from src/VeriSmith/Verilog/Preprocess.hs) | 4 | ||||
-rw-r--r-- | src/Verismith/Verilog/Quote.hs (renamed from src/VeriSmith/Verilog/Quote.hs) | 6 | ||||
-rw-r--r-- | src/Verismith/Verilog/Token.hs (renamed from src/VeriSmith/Verilog/Token.hs) | 4 |
34 files changed, 203 insertions, 203 deletions
diff --git a/src/VeriSmith.hs b/src/Verismith.hs index 6c1a1b5..e7d3ce6 100644 --- a/src/VeriSmith.hs +++ b/src/Verismith.hs @@ -1,6 +1,6 @@ {-| -Module : VeriSmith -Description : VeriSmith +Module : Verismith +Description : Verismith Copyright : (c) 2018-2019, Yann Herklotz License : BSD-3 Maintainer : yann [at] yannherklotz [dot] com @@ -10,7 +10,7 @@ Portability : POSIX {-# OPTIONS_GHC -Wno-unused-top-binds #-} -module VeriSmith +module Verismith ( defaultMain -- * Types , Opts(..) @@ -27,12 +27,12 @@ module VeriSmith , proceduralSrcIO , randomMod -- * Extra modules - , module VeriSmith.Verilog - , module VeriSmith.Config - , module VeriSmith.Circuit - , module VeriSmith.Sim - , module VeriSmith.Fuzz - , module VeriSmith.Report + , module Verismith.Verilog + , module Verismith.Config + , module Verismith.Circuit + , module Verismith.Sim + , module Verismith.Fuzz + , module Verismith.Report ) where @@ -58,17 +58,17 @@ import Prelude hiding (FilePath) import Shelly hiding (command) import Shelly.Lifted (liftSh) import System.Random (randomIO) -import VeriSmith.Circuit -import VeriSmith.Config -import VeriSmith.Fuzz -import VeriSmith.Generate -import VeriSmith.Reduce -import VeriSmith.Report -import VeriSmith.Result -import VeriSmith.Sim -import VeriSmith.Sim.Internal -import VeriSmith.Verilog -import VeriSmith.Verilog.Parser (parseSourceInfoFile) +import Verismith.Circuit +import Verismith.Config +import Verismith.Fuzz +import Verismith.Generate +import Verismith.Reduce +import Verismith.Report +import Verismith.Result +import Verismith.Sim +import Verismith.Sim.Internal +import Verismith.Verilog +import Verismith.Verilog.Parser (parseSourceInfoFile) data OptTool = TYosys | TXST @@ -315,7 +315,7 @@ opts = info ( fullDesc <> progDesc "Fuzz different simulators and synthesisers." <> header - "VeriSmith - A hardware simulator and synthesiser Verilog fuzzer." + "Verismith - A hardware simulator and synthesiser Verilog fuzzer." ) getConfig :: Maybe FilePath -> IO Config diff --git a/src/VeriSmith/Circuit.hs b/src/Verismith/Circuit.hs index aee0d57..81eec12 100644 --- a/src/VeriSmith/Circuit.hs +++ b/src/Verismith/Circuit.hs @@ -1,5 +1,5 @@ {-| -Module : VeriSmith.Circuit +Module : Verismith.Circuit Description : Definition of the circuit graph. Copyright : (c) 2018-2019, Yann Herklotz License : BSD-3 @@ -10,7 +10,7 @@ Portability : POSIX Definition of the circuit graph. -} -module VeriSmith.Circuit +module Verismith.Circuit ( -- * Circuit Gate(..) , Circuit(..) @@ -28,11 +28,11 @@ where import Control.Lens import Hedgehog (Gen) import qualified Hedgehog.Gen as Hog -import VeriSmith.Circuit.Base -import VeriSmith.Circuit.Gen -import VeriSmith.Circuit.Random -import VeriSmith.Verilog.AST -import VeriSmith.Verilog.Mutate +import Verismith.Circuit.Base +import Verismith.Circuit.Gen +import Verismith.Circuit.Random +import Verismith.Verilog.AST +import Verismith.Verilog.Mutate fromGraph :: Gen ModDecl fromGraph = do diff --git a/src/VeriSmith/Circuit/Base.hs b/src/Verismith/Circuit/Base.hs index ddcaf65..9a5ab34 100644 --- a/src/VeriSmith/Circuit/Base.hs +++ b/src/Verismith/Circuit/Base.hs @@ -1,5 +1,5 @@ {-| -Module : VeriSmith.Circuit.Base +Module : Verismith.Circuit.Base Description : Base types for the circuit module. Copyright : (c) 2019, Yann Herklotz Grave License : GPL-3 @@ -10,7 +10,7 @@ Portability : POSIX Base types for the circuit module. -} -module VeriSmith.Circuit.Base +module Verismith.Circuit.Base ( Gate(..) , Circuit(..) , CNode(..) diff --git a/src/VeriSmith/Circuit/Gen.hs b/src/Verismith/Circuit/Gen.hs index 1c4dd37..c5cb697 100644 --- a/src/VeriSmith/Circuit/Gen.hs +++ b/src/Verismith/Circuit/Gen.hs @@ -10,7 +10,7 @@ Portability : POSIX Generate verilog from circuit. -} -module VeriSmith.Circuit.Gen +module Verismith.Circuit.Gen ( generateAST ) where @@ -18,10 +18,10 @@ where import Data.Graph.Inductive (LNode, Node) import qualified Data.Graph.Inductive as G import Data.Maybe (catMaybes) -import VeriSmith.Circuit.Base -import VeriSmith.Circuit.Internal -import VeriSmith.Verilog.AST -import VeriSmith.Verilog.Mutate +import Verismith.Circuit.Base +import Verismith.Circuit.Internal +import Verismith.Verilog.AST +import Verismith.Verilog.Mutate -- | Converts a 'CNode' to an 'Identifier'. frNode :: Node -> Identifier diff --git a/src/VeriSmith/Circuit/Internal.hs b/src/Verismith/Circuit/Internal.hs index b746738..4de2252 100644 --- a/src/VeriSmith/Circuit/Internal.hs +++ b/src/Verismith/Circuit/Internal.hs @@ -1,5 +1,5 @@ {-| -Module : VeriSmith.Circuit.Internal +Module : Verismith.Circuit.Internal Description : Internal helpers for generation. Copyright : (c) 2018-2019, Yann Herklotz License : BSD-3 @@ -10,7 +10,7 @@ Portability : POSIX Internal helpers for generation. -} -module VeriSmith.Circuit.Internal +module Verismith.Circuit.Internal ( fromNode , filterGr , only diff --git a/src/VeriSmith/Circuit/Random.hs b/src/Verismith/Circuit/Random.hs index ca8cc26..0eabf56 100644 --- a/src/VeriSmith/Circuit/Random.hs +++ b/src/Verismith/Circuit/Random.hs @@ -1,5 +1,5 @@ {-| -Module : VeriSmith.Circuit.Random +Module : Verismith.Circuit.Random Description : Random generation for DAG Copyright : (c) 2018-2019, Yann Herklotz License : BSD-3 @@ -10,7 +10,7 @@ Portability : POSIX Define the random generation for the directed acyclic graph. -} -module VeriSmith.Circuit.Random +module Verismith.Circuit.Random ( rDups , rDupsCirc , randomDAG @@ -25,7 +25,7 @@ import Data.List (nub) import Hedgehog (Gen) import qualified Hedgehog.Gen as Hog import qualified Hedgehog.Range as Hog -import VeriSmith.Circuit.Base +import Verismith.Circuit.Base dupFolder :: (Eq a, Eq b) => Context a b -> [Context a b] -> [Context a b] dupFolder cont ns = unique cont : ns diff --git a/src/VeriSmith/Config.hs b/src/Verismith/Config.hs index adc3d19..9d37fd2 100644 --- a/src/VeriSmith/Config.hs +++ b/src/Verismith/Config.hs @@ -1,5 +1,5 @@ {-| -Module : VeriSmith.Config +Module : Verismith.Config Description : Configuration file format and parser. Copyright : (c) 2019, Yann Herklotz License : GPL-3 @@ -12,7 +12,7 @@ TOML Configuration file format and parser. {-# LANGUAGE TemplateHaskell #-} -module VeriSmith.Config +module Verismith.Config ( -- * TOML Configuration -- $conf Config(..) @@ -92,14 +92,14 @@ import Paths_verismith (version) import Shelly (toTextIgnore) import Toml (TomlCodec, (.=)) import qualified Toml -import VeriSmith.Sim.Quartus -import VeriSmith.Sim.Vivado -import VeriSmith.Sim.XST -import VeriSmith.Sim.Yosys +import Verismith.Sim.Quartus +import Verismith.Sim.Vivado +import Verismith.Sim.XST +import Verismith.Sim.Yosys -- $conf -- --- VeriSmith supports a TOML configuration file that can be passed using the @-c@ +-- Verismith supports a TOML configuration file that can be passed using the @-c@ -- flag or using the 'parseConfig' and 'encodeConfig' functions. The -- configuration can then be manipulated using the lenses that are also provided -- in this module. @@ -487,7 +487,7 @@ encodeConfigFile f = T.writeFile f . encodeConfig versionInfo :: String versionInfo = - "VeriSmith " + "Verismith " <> showVersion version <> " (" <> $(gitCommitDate) diff --git a/src/VeriSmith/Fuzz.hs b/src/Verismith/Fuzz.hs index 9331a5e..2e0c95f 100644 --- a/src/VeriSmith/Fuzz.hs +++ b/src/Verismith/Fuzz.hs @@ -1,5 +1,5 @@ {-| -Module : VeriSmith.Fuzz +Module : Verismith.Fuzz Description : Environment to run the simulator and synthesisers in a matrix. Copyright : (c) 2019, Yann Herklotz License : GPL-3 @@ -14,7 +14,7 @@ Environment to run the simulator and synthesisers in a matrix. {-# LANGUAGE FlexibleContexts #-} {-# LANGUAGE TemplateHaskell #-} -module VeriSmith.Fuzz +module Verismith.Fuzz ( Fuzz , fuzz , fuzzInDir @@ -54,16 +54,16 @@ import Prelude hiding (FilePath) import Shelly hiding (get) import Shelly.Lifted (MonadSh, liftSh) import System.FilePath.Posix (takeBaseName) -import VeriSmith.Config -import VeriSmith.Internal -import VeriSmith.Reduce -import VeriSmith.Report -import VeriSmith.Result -import VeriSmith.Sim.Icarus -import VeriSmith.Sim.Internal -import VeriSmith.Sim.Yosys -import VeriSmith.Verilog.AST -import VeriSmith.Verilog.CodeGen +import Verismith.Config +import Verismith.Internal +import Verismith.Reduce +import Verismith.Report +import Verismith.Result +import Verismith.Sim.Icarus +import Verismith.Sim.Internal +import Verismith.Sim.Yosys +import Verismith.Verilog.AST +import Verismith.Verilog.CodeGen data FuzzEnv = FuzzEnv { getSynthesisers :: ![SynthTool] , getSimulators :: ![SimTool] diff --git a/src/VeriSmith/Generate.hs b/src/Verismith/Generate.hs index 095baee..205a54a 100644 --- a/src/VeriSmith/Generate.hs +++ b/src/Verismith/Generate.hs @@ -1,5 +1,5 @@ {-| -Module : VeriSmith.Generate +Module : Verismith.Generate Description : Various useful generators. Copyright : (c) 2019, Yann Herklotz License : GPL-3 @@ -13,7 +13,7 @@ Various useful generators. {-# LANGUAGE TemplateHaskell #-} {-# OPTIONS_GHC -Wno-unused-imports #-} -module VeriSmith.Generate +module Verismith.Generate ( -- * Generation methods procedural , proceduralIO @@ -73,13 +73,13 @@ import qualified Data.Text as T import Hedgehog (Gen) import qualified Hedgehog.Gen as Hog import qualified Hedgehog.Range as Hog -import VeriSmith.Config -import VeriSmith.Internal -import VeriSmith.Verilog.AST -import VeriSmith.Verilog.BitVec -import VeriSmith.Verilog.Eval -import VeriSmith.Verilog.Internal -import VeriSmith.Verilog.Mutate +import Verismith.Config +import Verismith.Internal +import Verismith.Verilog.AST +import Verismith.Verilog.BitVec +import Verismith.Verilog.Eval +import Verismith.Verilog.Internal +import Verismith.Verilog.Mutate data Context = Context { _variables :: [Port] , _parameters :: [Parameter] diff --git a/src/VeriSmith/Internal.hs b/src/Verismith/Internal.hs index 86cb1f7..b47c924 100644 --- a/src/VeriSmith/Internal.hs +++ b/src/Verismith/Internal.hs @@ -1,5 +1,5 @@ {-| -Module : VeriSmith.Internal +Module : Verismith.Internal Description : Shared high level code used in the other modules internally. Copyright : (c) 2018-2019, Yann Herklotz License : BSD-3 @@ -10,7 +10,7 @@ Portability : POSIX Shared high level code used in the other modules internally. -} -module VeriSmith.Internal +module Verismith.Internal ( -- * Useful functions safe , showT diff --git a/src/VeriSmith/Reduce.hs b/src/Verismith/Reduce.hs index c57b457..69674cc 100644 --- a/src/VeriSmith/Reduce.hs +++ b/src/Verismith/Reduce.hs @@ -1,5 +1,5 @@ {-| -Module : VeriSmith.Reduce +Module : Verismith.Reduce Description : Test case reducer implementation. Copyright : (c) 2019, Yann Herklotz License : GPL-3 @@ -13,7 +13,7 @@ Test case reducer implementation. {-# LANGUAGE RankNTypes #-} {-# LANGUAGE ScopedTypeVariables #-} -module VeriSmith.Reduce +module Verismith.Reduce ( -- $strategy reduceWithScript , reduceSynth @@ -47,14 +47,14 @@ import Data.Text (Text) import Shelly ((<.>)) import qualified Shelly import Shelly.Lifted (MonadSh, liftSh) -import VeriSmith.Internal -import VeriSmith.Result -import VeriSmith.Sim -import VeriSmith.Sim.Internal -import VeriSmith.Verilog -import VeriSmith.Verilog.AST -import VeriSmith.Verilog.Mutate -import VeriSmith.Verilog.Parser +import Verismith.Internal +import Verismith.Result +import Verismith.Sim +import Verismith.Sim.Internal +import Verismith.Verilog +import Verismith.Verilog.AST +import Verismith.Verilog.Mutate +import Verismith.Verilog.Parser -- $strategy diff --git a/src/VeriSmith/Report.hs b/src/Verismith/Report.hs index fe680c3..b074be4 100644 --- a/src/VeriSmith/Report.hs +++ b/src/Verismith/Report.hs @@ -1,6 +1,6 @@ {-# LANGUAGE RankNTypes #-} {-| -Module : VeriSmith.Report +Module : Verismith.Report Description : Generate a report from a fuzz run. Copyright : (c) 2019, Yann Herklotz Grave License : GPL-3 @@ -13,7 +13,7 @@ Generate a report from a fuzz run. {-# LANGUAGE TemplateHaskell #-} -module VeriSmith.Report +module Verismith.Report ( SynthTool(..) , SynthStatus(..) , SynthResult(..) @@ -60,11 +60,11 @@ import Text.Blaze.Html (Html, (!)) import Text.Blaze.Html.Renderer.Text (renderHtml) import qualified Text.Blaze.Html5 as H import qualified Text.Blaze.Html5.Attributes as A -import VeriSmith.Config -import VeriSmith.Internal -import VeriSmith.Result -import VeriSmith.Sim -import VeriSmith.Sim.Internal +import Verismith.Config +import Verismith.Internal +import Verismith.Result +import Verismith.Sim +import Verismith.Sim.Internal -- | Common type alias for synthesis results type UResult = Result Failed () diff --git a/src/VeriSmith/Result.hs b/src/Verismith/Result.hs index 7bfbf9b..d8efd2f 100644 --- a/src/VeriSmith/Result.hs +++ b/src/Verismith/Result.hs @@ -1,5 +1,5 @@ {-| -Module : VeriSmith.Result +Module : Verismith.Result Description : Result monadic type. Copyright : (c) 2019, Yann Herklotz Grave License : GPL-3 @@ -9,7 +9,7 @@ Portability : POSIX Result monadic type. This is nearly equivalent to the transformers 'Error' type, but to have more control this is reimplemented with the instances that are -needed in "VeriSmith". +needed in "Verismith". -} {-# LANGUAGE FlexibleContexts #-} @@ -19,7 +19,7 @@ needed in "VeriSmith". {-# LANGUAGE TypeFamilies #-} {-# LANGUAGE UndecidableInstances #-} -module VeriSmith.Result +module Verismith.Result ( Result(..) , ResultT(..) , (<?>) diff --git a/src/VeriSmith/Sim.hs b/src/Verismith/Sim.hs index f0489d3..5e31985 100644 --- a/src/VeriSmith/Sim.hs +++ b/src/Verismith/Sim.hs @@ -1,5 +1,5 @@ {-| -Module : VeriSmith.Sim +Module : Verismith.Sim Description : Simulator implementations. Copyright : (c) 2019, Yann Herklotz Grave License : GPL-3 @@ -10,7 +10,7 @@ Portability : POSIX Simulator implementations. -} -module VeriSmith.Sim +module Verismith.Sim ( -- * Simulators -- ** Icarus @@ -42,10 +42,10 @@ module VeriSmith.Sim ) where -import VeriSmith.Sim.Icarus -import VeriSmith.Sim.Identity -import VeriSmith.Sim.Internal -import VeriSmith.Sim.Quartus -import VeriSmith.Sim.Vivado -import VeriSmith.Sim.XST -import VeriSmith.Sim.Yosys +import Verismith.Sim.Icarus +import Verismith.Sim.Identity +import Verismith.Sim.Internal +import Verismith.Sim.Quartus +import Verismith.Sim.Vivado +import Verismith.Sim.XST +import Verismith.Sim.Yosys diff --git a/src/VeriSmith/Sim/Icarus.hs b/src/Verismith/Sim/Icarus.hs index f104630..003f1de 100644 --- a/src/VeriSmith/Sim/Icarus.hs +++ b/src/Verismith/Sim/Icarus.hs @@ -1,5 +1,5 @@ {-| -Module : VeriSmith.Sim.Icarus +Module : Verismith.Sim.Icarus Description : Icarus verilog module. Copyright : (c) 2018-2019, Yann Herklotz License : BSD-3 @@ -10,7 +10,7 @@ Portability : POSIX Icarus verilog module. -} -module VeriSmith.Sim.Icarus +module Verismith.Sim.Icarus ( Icarus(..) , defaultIcarus , runSimIc @@ -39,13 +39,13 @@ import Numeric (readInt) import Prelude hiding (FilePath) import Shelly import Shelly.Lifted (liftSh) -import VeriSmith.Sim.Internal -import VeriSmith.Sim.Template -import VeriSmith.Verilog.AST -import VeriSmith.Verilog.BitVec -import VeriSmith.Verilog.CodeGen -import VeriSmith.Verilog.Internal -import VeriSmith.Verilog.Mutate +import Verismith.Sim.Internal +import Verismith.Sim.Template +import Verismith.Verilog.AST +import Verismith.Verilog.BitVec +import Verismith.Verilog.CodeGen +import Verismith.Verilog.Internal +import Verismith.Verilog.Mutate data Icarus = Icarus { icarusPath :: FilePath , vvpPath :: FilePath diff --git a/src/VeriSmith/Sim/Identity.hs b/src/Verismith/Sim/Identity.hs index cac230f..89c6b36 100644 --- a/src/VeriSmith/Sim/Identity.hs +++ b/src/Verismith/Sim/Identity.hs @@ -1,5 +1,5 @@ {-| -Module : VeriSmith.Sim.Identity +Module : Verismith.Sim.Identity Description : The identity simulator and synthesiser. Copyright : (c) 2019, Yann Herklotz Grave License : GPL-3 @@ -10,7 +10,7 @@ Portability : POSIX The identity simulator and synthesiser. -} -module VeriSmith.Sim.Identity +module Verismith.Sim.Identity ( Identity(..) , defaultIdentity ) @@ -21,9 +21,9 @@ import Data.Text (Text, unpack) import Prelude hiding (FilePath) import Shelly (FilePath) import Shelly.Lifted (writefile) -import VeriSmith.Sim.Internal -import VeriSmith.Verilog.AST -import VeriSmith.Verilog.CodeGen +import Verismith.Sim.Internal +import Verismith.Verilog.AST +import Verismith.Verilog.CodeGen data Identity = Identity { identityDesc :: {-# UNPACK #-} !Text , identityOutput :: {-# UNPACK #-} !FilePath diff --git a/src/VeriSmith/Sim/Internal.hs b/src/Verismith/Sim/Internal.hs index 017faad..bcbc3af 100644 --- a/src/VeriSmith/Sim/Internal.hs +++ b/src/Verismith/Sim/Internal.hs @@ -1,5 +1,5 @@ {-| -Module : VeriSmith.Sim.Internal +Module : Verismith.Sim.Internal Description : Class of the simulator. Copyright : (c) 2018-2019, Yann Herklotz License : BSD-3 @@ -12,7 +12,7 @@ Class of the simulator and the synthesize tool. {-# LANGUAGE DeriveFunctor #-} -module VeriSmith.Sim.Internal +module Verismith.Sim.Internal ( ResultSh , resultSh , Tool(..) @@ -54,9 +54,9 @@ import Prelude hiding (FilePath) import Shelly import Shelly.Lifted (MonadSh, liftSh) import System.FilePath.Posix (takeBaseName) -import VeriSmith.Internal -import VeriSmith.Result -import VeriSmith.Verilog.AST +import Verismith.Internal +import Verismith.Result +import Verismith.Verilog.AST -- | Tool class. class Tool a where @@ -100,7 +100,7 @@ renameSource :: (Synthesiser a) => a -> SourceInfo -> SourceInfo renameSource a src = src & infoSrc . _Wrapped . traverse . modId . _Wrapped %~ (<> toText a) --- | Type synonym for a 'ResultT' that will be used throughout 'VeriSmith'. This +-- | Type synonym for a 'ResultT' that will be used throughout 'Verismith'. This -- has instances for 'MonadSh' and 'MonadIO' if the 'Monad' it is parametrised -- with also has those instances. type ResultSh = ResultT Failed Sh @@ -170,7 +170,7 @@ logger t = do fn <- pwd currentTime <- liftIO getZonedTime echo - $ "VeriSmith " + $ "Verismith " <> T.pack (formatTime defaultTimeLocale "%H:%M:%S " currentTime) <> bname fn <> " - " diff --git a/src/VeriSmith/Sim/Quartus.hs b/src/Verismith/Sim/Quartus.hs index 6837133..5fb1e49 100644 --- a/src/VeriSmith/Sim/Quartus.hs +++ b/src/Verismith/Sim/Quartus.hs @@ -1,5 +1,5 @@ {-| -Module : VeriSmith.Sim.Quartus +Module : Verismith.Sim.Quartus Description : Quartus synthesiser implementation. Copyright : (c) 2019, Yann Herklotz Grave License : GPL-3 @@ -10,7 +10,7 @@ Portability : POSIX Quartus synthesiser implementation. -} -module VeriSmith.Sim.Quartus +module Verismith.Sim.Quartus ( Quartus(..) , defaultQuartus ) @@ -21,9 +21,9 @@ import Data.Text (Text, unpack) import Prelude hiding (FilePath) import Shelly import Shelly.Lifted (liftSh) -import VeriSmith.Sim.Internal -import VeriSmith.Verilog.AST -import VeriSmith.Verilog.CodeGen +import Verismith.Sim.Internal +import Verismith.Verilog.AST +import Verismith.Verilog.CodeGen data Quartus = Quartus { quartusBin :: !(Maybe FilePath) , quartusDesc :: {-# UNPACK #-} !Text diff --git a/src/VeriSmith/Sim/Template.hs b/src/Verismith/Sim/Template.hs index d232420..071e040 100644 --- a/src/VeriSmith/Sim/Template.hs +++ b/src/Verismith/Sim/Template.hs @@ -1,5 +1,5 @@ {-| -Module : VeriSmith.Sim.Template +Module : Verismith.Sim.Template Description : Template file for different configuration files Copyright : (c) 2019, Yann Herklotz License : GPL-3 @@ -12,7 +12,7 @@ Template file for different configuration files. {-# LANGUAGE QuasiQuotes #-} -module VeriSmith.Sim.Template +module Verismith.Sim.Template ( yosysSatConfig , yosysSimConfig , xstSynthConfig @@ -28,9 +28,9 @@ import qualified Data.Text as T import Prelude hiding (FilePath) import Shelly import Text.Shakespeare.Text (st) -import VeriSmith.Sim.Internal -import VeriSmith.Verilog.AST -import VeriSmith.Verilog.CodeGen +import Verismith.Sim.Internal +import Verismith.Verilog.AST +import Verismith.Verilog.CodeGen rename :: Text -> [Text] -> Text rename end entries = diff --git a/src/VeriSmith/Sim/Vivado.hs b/src/Verismith/Sim/Vivado.hs index e8d8f0d..2dad87d 100644 --- a/src/VeriSmith/Sim/Vivado.hs +++ b/src/Verismith/Sim/Vivado.hs @@ -1,5 +1,5 @@ {-| -Module : VeriSmith.Sim.Vivado +Module : Verismith.Sim.Vivado Description : Vivado Synthesiser implementation. Copyright : (c) 2019, Yann Herklotz Grave License : GPL-3 @@ -10,7 +10,7 @@ Portability : POSIX Vivado Synthesiser implementation. -} -module VeriSmith.Sim.Vivado +module Verismith.Sim.Vivado ( Vivado(..) , defaultVivado ) @@ -21,10 +21,10 @@ import Data.Text (Text, unpack) import Prelude hiding (FilePath) import Shelly import Shelly.Lifted (liftSh) -import VeriSmith.Sim.Internal -import VeriSmith.Sim.Template -import VeriSmith.Verilog.AST -import VeriSmith.Verilog.CodeGen +import Verismith.Sim.Internal +import Verismith.Sim.Template +import Verismith.Verilog.AST +import Verismith.Verilog.CodeGen data Vivado = Vivado { vivadoBin :: !(Maybe FilePath) , vivadoDesc :: {-# UNPACK #-} !Text diff --git a/src/VeriSmith/Sim/XST.hs b/src/Verismith/Sim/XST.hs index 30a4b0b..9144ba7 100644 --- a/src/VeriSmith/Sim/XST.hs +++ b/src/Verismith/Sim/XST.hs @@ -1,5 +1,5 @@ {-| -Module : VeriSmith.Sim.XST +Module : Verismith.Sim.XST Description : XST (ise) simulator implementation. Copyright : (c) 2018-2019, Yann Herklotz License : BSD-3 @@ -12,7 +12,7 @@ XST (ise) simulator implementation. {-# LANGUAGE QuasiQuotes #-} -module VeriSmith.Sim.XST +module Verismith.Sim.XST ( XST(..) , defaultXST ) @@ -24,10 +24,10 @@ import Prelude hiding (FilePath) import Shelly import Shelly.Lifted (liftSh) import Text.Shakespeare.Text (st) -import VeriSmith.Sim.Internal -import VeriSmith.Sim.Template -import VeriSmith.Verilog.AST -import VeriSmith.Verilog.CodeGen +import Verismith.Sim.Internal +import Verismith.Sim.Template +import Verismith.Verilog.AST +import Verismith.Verilog.CodeGen data XST = XST { xstBin :: !(Maybe FilePath) , xstDesc :: {-# UNPACK #-} !Text diff --git a/src/VeriSmith/Sim/Yosys.hs b/src/Verismith/Sim/Yosys.hs index 1f583a8..9805140 100644 --- a/src/VeriSmith/Sim/Yosys.hs +++ b/src/Verismith/Sim/Yosys.hs @@ -1,5 +1,5 @@ {-| -Module : VeriSmith.Sim.Yosys +Module : Verismith.Sim.Yosys Description : Yosys simulator implementation. Copyright : (c) 2018-2019, Yann Herklotz License : BSD-3 @@ -12,7 +12,7 @@ Yosys simulator implementation. {-# LANGUAGE QuasiQuotes #-} -module VeriSmith.Sim.Yosys +module Verismith.Sim.Yosys ( Yosys(..) , defaultYosys , runEquiv @@ -28,12 +28,12 @@ import Prelude hiding (FilePath) import Shelly import Shelly.Lifted (liftSh) import Text.Shakespeare.Text (st) -import VeriSmith.Result -import VeriSmith.Sim.Internal -import VeriSmith.Sim.Template -import VeriSmith.Verilog.AST -import VeriSmith.Verilog.CodeGen -import VeriSmith.Verilog.Mutate +import Verismith.Result +import Verismith.Sim.Internal +import Verismith.Sim.Template +import Verismith.Verilog.AST +import Verismith.Verilog.CodeGen +import Verismith.Verilog.Mutate data Yosys = Yosys { yosysBin :: !(Maybe FilePath) , yosysDesc :: {-# UNPACK #-} !Text diff --git a/src/VeriSmith/Verilog.hs b/src/Verismith/Verilog.hs index 6e7851c..f3d9e85 100644 --- a/src/VeriSmith/Verilog.hs +++ b/src/Verismith/Verilog.hs @@ -1,5 +1,5 @@ {-| -Module : VeriSmith.Verilog +Module : Verismith.Verilog Description : Verilog implementation with random generation and mutations. Copyright : (c) 2019, Yann Herklotz Grave License : GPL-3 @@ -12,7 +12,7 @@ Verilog implementation with random generation and mutations. {-# LANGUAGE QuasiQuotes #-} -module VeriSmith.Verilog +module Verismith.Verilog ( SourceInfo(..) , Verilog(..) , parseVerilog @@ -100,7 +100,7 @@ module VeriSmith.Verilog ) where -import VeriSmith.Verilog.AST -import VeriSmith.Verilog.CodeGen -import VeriSmith.Verilog.Parser -import VeriSmith.Verilog.Quote +import Verismith.Verilog.AST +import Verismith.Verilog.CodeGen +import Verismith.Verilog.Parser +import Verismith.Verilog.Quote diff --git a/src/VeriSmith/Verilog/AST.hs b/src/Verismith/Verilog/AST.hs index 78bad45..699d87a 100644 --- a/src/VeriSmith/Verilog/AST.hs +++ b/src/Verismith/Verilog/AST.hs @@ -1,5 +1,5 @@ {-| -Module : VeriSmith.Verilog.AST +Module : Verismith.Verilog.AST Description : Definition of the Verilog AST types. Copyright : (c) 2018-2019, Yann Herklotz License : BSD-3 @@ -22,7 +22,7 @@ Defines the types to build a Verilog AST. {-# LANGUAGE TemplateHaskell #-} {-# LANGUAGE TypeFamilies #-} -module VeriSmith.Verilog.AST +module Verismith.Verilog.AST ( -- * Top level types SourceInfo(..) , infoTop @@ -150,7 +150,7 @@ import Data.String (IsString, fromString) import Data.Text (Text, pack) import Data.Traversable (sequenceA) import GHC.Generics (Generic) -import VeriSmith.Verilog.BitVec +import Verismith.Verilog.BitVec -- | Identifier in Verilog. This is just a string of characters that can either -- be lowercase and uppercase for now. This might change in the future though, diff --git a/src/VeriSmith/Verilog/BitVec.hs b/src/Verismith/Verilog/BitVec.hs index dab9e2c..bc594a3 100644 --- a/src/VeriSmith/Verilog/BitVec.hs +++ b/src/Verismith/Verilog/BitVec.hs @@ -1,5 +1,5 @@ {-| -Module : VeriSmith.Verilog.BitVec +Module : Verismith.Verilog.BitVec Description : Unsigned BitVec implementation. Copyright : (c) 2019, Yann Herklotz Grave License : GPL-3 @@ -17,7 +17,7 @@ Unsigned BitVec implementation. {-# LANGUAGE DeriveGeneric #-} {-# LANGUAGE DeriveTraversable #-} -module VeriSmith.Verilog.BitVec +module Verismith.Verilog.BitVec ( BitVecF(..) , BitVec , bitVec diff --git a/src/VeriSmith/Verilog/CodeGen.hs b/src/Verismith/Verilog/CodeGen.hs index 1e94472..ca48a33 100644 --- a/src/VeriSmith/Verilog/CodeGen.hs +++ b/src/Verismith/Verilog/CodeGen.hs @@ -1,5 +1,5 @@ {-| -Module : VeriSmith.Verilog.CodeGen +Module : Verismith.Verilog.CodeGen Description : Code generation for Verilog AST. Copyright : (c) 2018-2019, Yann Herklotz License : BSD-3 @@ -8,13 +8,13 @@ Stability : experimental Portability : POSIX This module generates the code from the Verilog AST defined in -"VeriSmith.Verilog.AST". +"Verismith.Verilog.AST". -} {-# LANGUAGE DeriveDataTypeable #-} {-# LANGUAGE FlexibleInstances #-} -module VeriSmith.Verilog.CodeGen +module Verismith.Verilog.CodeGen ( -- * Code Generation GenVerilog(..) , Source(..) @@ -28,9 +28,9 @@ import Data.Text (Text) import qualified Data.Text as T import Data.Text.Prettyprint.Doc import Numeric (showHex) -import VeriSmith.Internal hiding (comma) -import VeriSmith.Verilog.AST -import VeriSmith.Verilog.BitVec +import Verismith.Internal hiding (comma) +import Verismith.Verilog.AST +import Verismith.Verilog.BitVec -- | 'Source' class which determines that source code is able to be generated -- from the data structure using 'genSource'. This will be stored in 'Text' and diff --git a/src/VeriSmith/Verilog/Eval.hs b/src/Verismith/Verilog/Eval.hs index 1ebaa80..cbc2563 100644 --- a/src/VeriSmith/Verilog/Eval.hs +++ b/src/Verismith/Verilog/Eval.hs @@ -1,5 +1,5 @@ {-| -Module : VeriSmith.Verilog.Eval +Module : Verismith.Verilog.Eval Description : Evaluation of Verilog expressions and statements. Copyright : (c) 2019, Yann Herklotz Grave License : GPL-3 @@ -10,7 +10,7 @@ Portability : POSIX Evaluation of Verilog expressions and statements. -} -module VeriSmith.Verilog.Eval +module Verismith.Verilog.Eval ( evaluateConst , resize ) @@ -20,8 +20,8 @@ import Data.Bits import Data.Foldable (fold) import Data.Functor.Foldable hiding (fold) import Data.Maybe (listToMaybe) -import VeriSmith.Verilog.AST -import VeriSmith.Verilog.BitVec +import Verismith.Verilog.AST +import Verismith.Verilog.BitVec type Bindings = [Parameter] diff --git a/src/VeriSmith/Verilog/Internal.hs b/src/Verismith/Verilog/Internal.hs index ed91b12..b3bf07a 100644 --- a/src/VeriSmith/Verilog/Internal.hs +++ b/src/Verismith/Verilog/Internal.hs @@ -1,5 +1,5 @@ {-| -Module : VeriSmith.Verilog.Internal +Module : Verismith.Verilog.Internal Description : Defaults and common functions. Copyright : (c) 2018-2019, Yann Herklotz License : BSD-3 @@ -10,7 +10,7 @@ Portability : POSIX Defaults and common functions. -} -module VeriSmith.Verilog.Internal +module Verismith.Verilog.Internal ( regDecl , wireDecl , emptyMod @@ -30,7 +30,7 @@ where import Control.Lens import Data.Text (Text) -import VeriSmith.Verilog.AST +import Verismith.Verilog.AST regDecl :: Identifier -> ModItem regDecl i = Decl Nothing (Port Reg False (Range 1 0) i) Nothing diff --git a/src/VeriSmith/Verilog/Lex.x b/src/Verismith/Verilog/Lex.x index 3d1dd8d..9892714 100644 --- a/src/VeriSmith/Verilog/Lex.x +++ b/src/Verismith/Verilog/Lex.x @@ -1,11 +1,11 @@ -- -*- haskell -*- { {-# OPTIONS_GHC -w #-} -module VeriSmith.Verilog.Lex +module Verismith.Verilog.Lex ( alexScanTokens ) where -import VeriSmith.Verilog.Token +import Verismith.Verilog.Token } diff --git a/src/VeriSmith/Verilog/Mutate.hs b/src/Verismith/Verilog/Mutate.hs index 58675e3..2f17de5 100644 --- a/src/VeriSmith/Verilog/Mutate.hs +++ b/src/Verismith/Verilog/Mutate.hs @@ -1,5 +1,5 @@ {-| -Module : VeriSmith.Verilog.Mutate +Module : Verismith.Verilog.Mutate Description : Functions to mutate the Verilog AST. Copyright : (c) 2018-2019, Yann Herklotz License : BSD-3 @@ -7,13 +7,13 @@ Maintainer : yann [at] yannherklotz [dot] com Stability : experimental Portability : POSIX -Functions to mutate the Verilog AST from "VeriSmith.Verilog.AST" to generate more +Functions to mutate the Verilog AST from "Verismith.Verilog.AST" to generate more random patterns, such as nesting wires instead of creating new ones. -} {-# LANGUAGE FlexibleInstances #-} -module VeriSmith.Verilog.Mutate +module Verismith.Verilog.Mutate ( Mutate(..) , inPort , findAssign @@ -45,12 +45,12 @@ import Data.Foldable (fold) import Data.Maybe (catMaybes, fromMaybe) import Data.Text (Text) import qualified Data.Text as T -import VeriSmith.Circuit.Internal -import VeriSmith.Internal -import VeriSmith.Verilog.AST -import VeriSmith.Verilog.BitVec -import VeriSmith.Verilog.CodeGen -import VeriSmith.Verilog.Internal +import Verismith.Circuit.Internal +import Verismith.Internal +import Verismith.Verilog.AST +import Verismith.Verilog.BitVec +import Verismith.Verilog.CodeGen +import Verismith.Verilog.Internal class Mutate a where mutExpr :: (Expr -> Expr) -> a -> a @@ -210,7 +210,7 @@ allVars m = <> (m ^.. modInPorts . traverse . portName) -- $setup --- >>> import VeriSmith.Verilog.CodeGen +-- >>> import Verismith.Verilog.CodeGen -- >>> let m = (ModDecl (Identifier "m") [Port Wire False 5 (Identifier "y")] [Port Wire False 5 "x"] [] []) -- >>> let main = (ModDecl "main" [] [] [] []) diff --git a/src/VeriSmith/Verilog/Parser.hs b/src/Verismith/Verilog/Parser.hs index 8d2b729..a6eaf24 100644 --- a/src/VeriSmith/Verilog/Parser.hs +++ b/src/Verismith/Verilog/Parser.hs @@ -1,5 +1,5 @@ {-| -Module : VeriSmith.Verilog.Parser +Module : Verismith.Verilog.Parser Description : Minimal Verilog parser to reconstruct the AST. Copyright : (c) 2019, Yann Herklotz License : GPL-3 @@ -11,7 +11,7 @@ Minimal Verilog parser to reconstruct the AST. This parser does not support the whole Verilog syntax, as the AST does not support it either. -} -module VeriSmith.Verilog.Parser +module Verismith.Verilog.Parser ( -- * Parser parseVerilog , parseVerilogFile @@ -38,13 +38,13 @@ import qualified Data.Text as T import qualified Data.Text.IO as T import Text.Parsec hiding (satisfy) import Text.Parsec.Expr -import VeriSmith.Internal -import VeriSmith.Verilog.AST -import VeriSmith.Verilog.BitVec -import VeriSmith.Verilog.Internal -import VeriSmith.Verilog.Lex -import VeriSmith.Verilog.Preprocess -import VeriSmith.Verilog.Token +import Verismith.Internal +import Verismith.Verilog.AST +import Verismith.Verilog.BitVec +import Verismith.Verilog.Internal +import Verismith.Verilog.Lex +import Verismith.Verilog.Preprocess +import Verismith.Verilog.Token type Parser = Parsec [Token] () diff --git a/src/VeriSmith/Verilog/Preprocess.hs b/src/Verismith/Verilog/Preprocess.hs index c30252b..91356f1 100644 --- a/src/VeriSmith/Verilog/Preprocess.hs +++ b/src/Verismith/Verilog/Preprocess.hs @@ -1,5 +1,5 @@ {-| -Module : VeriSmith.Verilog.Preprocess +Module : Verismith.Verilog.Preprocess Description : Simple preprocessor for `define and comments. Copyright : (c) 2011-2015 Tom Hawkins, 2019 Yann Herklotz License : GPL-3 @@ -14,7 +14,7 @@ The code is from https://github.com/tomahawkins/verilog. Edits to the original code are warning fixes and formatting changes. -} -module VeriSmith.Verilog.Preprocess +module Verismith.Verilog.Preprocess ( uncomment , preprocess ) diff --git a/src/VeriSmith/Verilog/Quote.hs b/src/Verismith/Verilog/Quote.hs index 3815fe6..879b8fd 100644 --- a/src/VeriSmith/Verilog/Quote.hs +++ b/src/Verismith/Verilog/Quote.hs @@ -1,5 +1,5 @@ {-| -Module : VeriSmith.Verilog.Quote +Module : Verismith.Verilog.Quote Description : QuasiQuotation for verilog code in Haskell. Copyright : (c) 2019, Yann Herklotz Grave License : GPL-3 @@ -12,7 +12,7 @@ QuasiQuotation for verilog code in Haskell. {-# LANGUAGE TemplateHaskell #-} -module VeriSmith.Verilog.Quote +module Verismith.Verilog.Quote ( verilog ) where @@ -22,7 +22,7 @@ import qualified Data.Text as T import qualified Language.Haskell.TH as TH import Language.Haskell.TH.Quote import Language.Haskell.TH.Syntax -import VeriSmith.Verilog.Parser +import Verismith.Verilog.Parser liftDataWithText :: Data a => a -> Q Exp liftDataWithText = dataToExpQ $ fmap liftText . cast diff --git a/src/VeriSmith/Verilog/Token.hs b/src/Verismith/Verilog/Token.hs index 590672e..b303e18 100644 --- a/src/VeriSmith/Verilog/Token.hs +++ b/src/Verismith/Verilog/Token.hs @@ -1,5 +1,5 @@ {-| -Module : VeriSmith.Verilog.Token +Module : Verismith.Verilog.Token Description : Tokens for Verilog parsing. Copyright : (c) 2019, Yann Herklotz Grave License : GPL-3 @@ -10,7 +10,7 @@ Portability : POSIX Tokens for Verilog parsing. -} -module VeriSmith.Verilog.Token +module Verismith.Verilog.Token ( Token(..) , TokenName(..) , Position(..) |