1 files changed, 96 insertions, 1 deletions

diff --git a/test/Reduce.hs b/test/Reduce.hs
index 9c59e48..bc47d94 100644
--- a/test/Reduce.hs
+++ b/test/Reduce.hs
@@ -17,7 +17,7 @@ module Reduce
     )
 where
 
-import           Data.List        ((\\))
+import           Data.List                      ( (\\) )
 import           Test.Tasty
 import           Test.Tasty.HUnit
 import           VeriFuzz
@@ -29,6 +29,7 @@ reduceUnitTests = testGroup
     [ moduleReducerTest
     , modItemReduceTest
     , halveStatementsTest
+    , statementReducerTest
     , activeWireTest
     , cleanTest
     , cleanAllTest
@@ -52,6 +53,7 @@ module top;
   reg h;
   wire i;
   wire j;
+  wire clk;
   initial d <= a;
 
   always @* begin
@@ -62,6 +64,8 @@ module top;
     end
   end
 
+  always @(posedge clk);
+
   assign b = g;
 endmodule
 |]
@@ -74,6 +78,7 @@ module top;
   reg f;
   reg g;
   reg h;
+  wire clk;
   initial d <= a;
 
   always @* begin
@@ -84,6 +89,8 @@ module top;
     end
   end
 
+  always @(posedge clk);
+
   assign b = g;
 endmodule
 |]
@@ -366,6 +373,94 @@ endmodule
 |])
 
 -- brittany-disable-next-binding
+statementReducerTest :: TestTree
+statementReducerTest = testCase "Statement reducer" $ do
+    GenVerilog <$> halveStatements "top" srcInfo1 @?= fmap GenVerilog golden1
+    GenVerilog <$> halveStatements "top" srcInfo2 @?= fmap GenVerilog golden2
+    where
+        srcInfo1 = SourceInfo "top" [verilog|
+module top(y, x);
+  output wire [4:0] y;
+  input wire [4:0] x;
+
+  always @(posedge clk) begin
+    a <= 1;
+    b <= 2;
+    c <= 3;
+    d <= 4;
+  end
+
+  always @(posedge clk) begin
+    a <= 1;
+    b <= 2;
+    c <= 3;
+    d <= 4;
+  end
+endmodule
+|]
+        golden1 = Dual (SourceInfo "top" [verilog|
+module top(y, x);
+  output wire [4:0] y;
+  input wire [4:0] x;
+
+  always @(posedge clk) begin
+    a <= 1;
+    b <= 2;
+  end
+
+  always @(posedge clk) begin
+    a <= 1;
+    b <= 2;
+  end
+endmodule
+|]) $ SourceInfo "top" [verilog|
+module top(y, x);
+  output wire [4:0] y;
+  input wire [4:0] x;
+
+  always @(posedge clk) begin
+    c <= 3;
+    d <= 4;
+  end
+
+  always @(posedge clk) begin
+    c <= 3;
+    d <= 4;
+  end
+endmodule
+|]
+        srcInfo2 = SourceInfo "top" [verilog|
+module top(y, x);
+  output wire [4:0] y;
+  input wire [4:0] x;
+
+  always @(posedge clk) begin
+    if (x)
+      y <= 2;
+    else
+      y <= 3;
+  end
+endmodule
+|]
+        golden2 = Dual (SourceInfo "top" [verilog|
+module top(y, x);
+  output wire [4:0] y;
+  input wire [4:0] x;
+
+  always @(posedge clk)
+      y <= 2;
+endmodule
+|]) $ SourceInfo "top" [verilog|
+module top(y, x);
+  output wire [4:0] y;
+  input wire [4:0] x;
+
+  always @(posedge clk)
+      y <= 3;
+endmodule
+|]
+
+-- brittany-disable-next-binding
 moduleReducerTest :: TestTree
 moduleReducerTest = testCase "Module reducer" $ do
     halveModules srcInfo1 @?= golden1