diff options
Diffstat (limited to 'test')
| -rw-r--r-- | test/Doctest.hs | 7 | ||||
| -rw-r--r-- | test/Parser.hs | 13 | ||||
| -rw-r--r-- | test/Property.hs | 27 | ||||
| -rw-r--r-- | test/Reduce.hs | 97 | ||||
| -rw-r--r-- | test/Unit.hs | 6 |
5 files changed, 130 insertions, 20 deletions
diff --git a/test/Doctest.hs b/test/Doctest.hs index 7463dfe..9dc22a4 100644 --- a/test/Doctest.hs +++ b/test/Doctest.hs @@ -1,7 +1,10 @@ module Main where -import Build_doctests (flags, module_sources, pkgs) -import Test.DocTest (doctest) +import Build_doctests ( flags + , module_sources + , pkgs + ) +import Test.DocTest ( doctest ) main :: IO () main = doctest args where args = flags ++ pkgs ++ module_sources diff --git a/test/Parser.hs b/test/Parser.hs index 03cc3a6..84f1906 100644 --- a/test/Parser.hs +++ b/test/Parser.hs @@ -17,10 +17,15 @@ module Parser where import Control.Lens -import Data.Either (either, isRight) -import Hedgehog (Gen, Property, (===)) -import qualified Hedgehog as Hog -import qualified Hedgehog.Gen as Hog +import Data.Either ( either + , isRight + ) +import Hedgehog ( Gen + , Property + , (===) + ) +import qualified Hedgehog as Hog +import qualified Hedgehog.Gen as Hog import Test.Tasty import Test.Tasty.Hedgehog import Test.Tasty.HUnit diff --git a/test/Property.hs b/test/Property.hs index 001c7d3..4e17695 100644 --- a/test/Property.hs +++ b/test/Property.hs @@ -11,16 +11,23 @@ module Property ) where -import Data.Either (either, isRight) -import qualified Data.Graph.Inductive as G -import Data.Text (Text) -import Hedgehog (Gen, Property, (===)) -import qualified Hedgehog as Hog -import Hedgehog.Function (Arg, Vary) -import qualified Hedgehog.Function as Hog -import qualified Hedgehog.Gen as Hog -import qualified Hedgehog.Range as Hog -import Parser (parserTests) +import Data.Either ( either + , isRight + ) +import qualified Data.Graph.Inductive as G +import Data.Text ( Text ) +import Hedgehog ( Gen + , Property + , (===) + ) +import qualified Hedgehog as Hog +import Hedgehog.Function ( Arg + , Vary + ) +import qualified Hedgehog.Function as Hog +import qualified Hedgehog.Gen as Hog +import qualified Hedgehog.Range as Hog +import Parser ( parserTests ) import Test.Tasty import Test.Tasty.Hedgehog import Text.Parsec diff --git a/test/Reduce.hs b/test/Reduce.hs index 9c59e48..bc47d94 100644 --- a/test/Reduce.hs +++ b/test/Reduce.hs @@ -17,7 +17,7 @@ module Reduce ) where -import Data.List ((\\)) +import Data.List ( (\\) ) import Test.Tasty import Test.Tasty.HUnit import VeriFuzz @@ -29,6 +29,7 @@ reduceUnitTests = testGroup [ moduleReducerTest , modItemReduceTest , halveStatementsTest + , statementReducerTest , activeWireTest , cleanTest , cleanAllTest @@ -52,6 +53,7 @@ module top; reg h; wire i; wire j; + wire clk; initial d <= a; always @* begin @@ -62,6 +64,8 @@ module top; end end + always @(posedge clk); + assign b = g; endmodule |] @@ -74,6 +78,7 @@ module top; reg f; reg g; reg h; + wire clk; initial d <= a; always @* begin @@ -84,6 +89,8 @@ module top; end end + always @(posedge clk); + assign b = g; endmodule |] @@ -366,6 +373,94 @@ endmodule |]) -- brittany-disable-next-binding +statementReducerTest :: TestTree +statementReducerTest = testCase "Statement reducer" $ do + GenVerilog <$> halveStatements "top" srcInfo1 @?= fmap GenVerilog golden1 + GenVerilog <$> halveStatements "top" srcInfo2 @?= fmap GenVerilog golden2 + where + srcInfo1 = SourceInfo "top" [verilog| +module top(y, x); + output wire [4:0] y; + input wire [4:0] x; + + always @(posedge clk) begin + a <= 1; + b <= 2; + c <= 3; + d <= 4; + end + + always @(posedge clk) begin + a <= 1; + b <= 2; + c <= 3; + d <= 4; + end +endmodule +|] + golden1 = Dual (SourceInfo "top" [verilog| +module top(y, x); + output wire [4:0] y; + input wire [4:0] x; + + always @(posedge clk) begin + a <= 1; + b <= 2; + end + + always @(posedge clk) begin + a <= 1; + b <= 2; + end +endmodule +|]) $ SourceInfo "top" [verilog| +module top(y, x); + output wire [4:0] y; + input wire [4:0] x; + + always @(posedge clk) begin + c <= 3; + d <= 4; + end + + always @(posedge clk) begin + c <= 3; + d <= 4; + end +endmodule +|] + srcInfo2 = SourceInfo "top" [verilog| +module top(y, x); + output wire [4:0] y; + input wire [4:0] x; + + always @(posedge clk) begin + if (x) + y <= 2; + else + y <= 3; + end +endmodule +|] + golden2 = Dual (SourceInfo "top" [verilog| +module top(y, x); + output wire [4:0] y; + input wire [4:0] x; + + always @(posedge clk) + y <= 2; +endmodule +|]) $ SourceInfo "top" [verilog| +module top(y, x); + output wire [4:0] y; + input wire [4:0] x; + + always @(posedge clk) + y <= 3; +endmodule +|] + +-- brittany-disable-next-binding moduleReducerTest :: TestTree moduleReducerTest = testCase "Module reducer" $ do halveModules srcInfo1 @?= golden1 diff --git a/test/Unit.hs b/test/Unit.hs index 84508c4..aaffe09 100644 --- a/test/Unit.hs +++ b/test/Unit.hs @@ -4,9 +4,9 @@ module Unit where import Control.Lens -import Data.List.NonEmpty (NonEmpty (..)) -import Parser (parseUnitTests) -import Reduce (reduceUnitTests) +import Data.List.NonEmpty ( NonEmpty(..) ) +import Parser ( parseUnitTests ) +import Reduce ( reduceUnitTests ) import Test.Tasty import Test.Tasty.HUnit import VeriFuzz |