| Commit message (Expand) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| * | Formatting | Yann Herklotz | 2019-01-01 | 1 | -3/+3 | |
| * | Remove empty statement and Monoid instance | Yann Herklotz | 2019-01-01 | 1 | -4/+0 | |
| * | Fix Semigroup instances | Yann Herklotz | 2019-01-01 | 1 | -4/+8 | |
| * | Use Monoid Statement instance to make code more concise | Yann Herklotz | 2019-01-01 | 1 | -5/+3 | |
| * | Add documentation | Yann Herklotz | 2019-01-01 | 1 | -0/+10 | |
| * | Add string instance to expression | Yann Herklotz | 2019-01-01 | 1 | -12/+42 | |
| * | Add missing case in function | Yann Herklotz | 2018-12-31 | 1 | -0/+2 | |
| * | Add show instance and add concat to reglval | Yann Herklotz | 2018-12-31 | 4 | -42/+88 | |
| * | Fix build errors | Yann Herklotz | 2018-12-31 | 2 | -2/+5 | |
| * | Remove sep and fromList in favour of fold | Yann Herklotz | 2018-12-31 | 3 | -26/+7 | |
| * | Separate arbitrary from types | Yann Herklotz | 2018-12-31 | 1 | -0/+184 | |
| * | Adding code to Icarus | Yann Herklotz | 2018-12-31 | 1 | -3/+15 | |
| * | Large refactor | Yann Herklotz | 2018-12-31 | 9 | -345/+171 | |
| * | Finish module instantiation | Yann Herklotz | 2018-12-31 | 3 | -6/+16 | |
| * | Add direction to Decl and add doctest | Yann Herklotz | 2018-12-31 | 4 | -11/+26 | |
| * | [Fix #17] Add size to ports | Yann Herklotz | 2018-12-31 | 2 | -5/+13 | |
| * | Add doctest test | Yann Herklotz | 2018-12-31 | 1 | -0/+8 | |
| * | Adding doctest suite | Yann Herklotz | 2018-12-31 | 2 | -0/+15 | |
| * | Fix dot generation | Yann Herklotz | 2018-12-31 | 2 | -4/+7 | |
| * | Delete lib folder | Yann Herklotz | 2018-12-30 | 1 | -0/+0 | |
| * | [Fix #13, Fix #15] Fix type errors and add inst functions | Yann Herklotz | 2018-12-30 | 4 | -14/+17 | |
| * | Change modPort type from Maybe to List | Yann Herklotz | 2018-12-30 | 1 | -1/+1 | |
| * | Upgrade travis version | Yann Herklotz | 2018-12-30 | 1 | -2/+2 | |
| * | Upgrade stack version | Yann Herklotz | 2018-12-30 | 4 | -11/+8 | |
| * | [Fix #14] Add size to Port type | Yann Herklotz | 2018-12-30 | 4 | -14/+23 | |
| * | Move helper functions | Yann Herklotz | 2018-12-30 | 4 | -6/+8 | |
| * | Add remove duplicates | Yann Herklotz | 2018-12-29 | 3 | -8/+20 | |
| * | Add internal function for fix | Yann Herklotz | 2018-12-29 | 1 | -0/+6 | |
| * | Fix verilog output for output port | Yann Herklotz | 2018-12-29 | 1 | -1/+1 | |
| * | Make tests a bit nicer | Yann Herklotz | 2018-12-29 | 1 | -5/+6 | |
| * | Add tests for new generation method | Yann Herklotz | 2018-12-29 | 2 | -13/+16 | |
| * | Add alternative generation method | Yann Herklotz | 2018-12-29 | 1 | -0/+29 | |
| * | Add new generation method | Yann Herklotz | 2018-12-29 | 2 | -20/+25 | |
| * | Add missing dependencies | Yann Herklotz | 2018-12-29 | 2 | -7/+12 | |
| * | Style changes | Yann Herklotz | 2018-12-29 | 1 | -7/+7 | |
| * | Remove run_sim script | Yann Herklotz | 2018-12-29 | 1 | -10/+0 | |
| * | Back to minimal | Yann Herklotz | 2018-12-29 | 1 | -0/+1 | |
| * | Remove language specification as it is somehow slower | Yann Herklotz | 2018-12-29 | 1 | -1/+0 | |
| * | Triggering travis again | Yann Herklotz | 2018-12-29 | 0 | -0/+0 | |
| * | Minimal language added | Yann Herklotz | 2018-12-29 | 1 | -0/+1 | |
| * | Add link to README | Yann Herklotz | 2018-12-29 | 2 | -2/+2 | |
| * | Add more info to README | Yann Herklotz | 2018-12-29 | 1 | -3/+8 | |
| * | Remove useless dependencies | Yann Herklotz | 2018-12-29 | 1 | -5/+4 | |
| * | Add badge | Yann Herklotz | 2018-12-29 | 1 | -0/+3 | |
| * | Downgrading ghc | Yann Herklotz | 2018-12-29 | 1 | -2/+2 | |
| * | Trigger travis | Yann Herklotz | 2018-12-29 | 0 | -0/+0 | |
| * | Add travis.yml file | Yann Herklotz | 2018-12-29 | 1 | -0/+24 | |
| * | Make generation more controlled | Yann Herklotz | 2018-12-29 | 2 | -8/+10 | |
| * | Rearrange instances | Yann Herklotz | 2018-12-29 | 1 | -5/+5 | |
| * | Changes to the API | Yann Herklotz | 2018-12-29 | 6 | -43/+64 | |
 |
index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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