| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | Fix setup script for new aws | Yann Herklotz | 2019-05-12 | 1 | -3/+10 | |
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| * | Add randomisation of config file with --randomise | Yann Herklotz | 2019-05-12 | 2 | -6/+58 | |
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| * | Remove warnings | Yann Herklotz | 2019-05-12 | 1 | -118/+119 | |
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| * | Add more dependencies to build Yosys on EC2 | Yann Herklotz | 2019-05-12 | 3 | -12/+8 | |
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| * | Add defaultMain | Yann Herklotz | 2019-05-12 | 2 | -245/+245 | |
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| * | Add Quote.hs | Yann Herklotz | 2019-05-12 | 1 | -0/+49 | |
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| * | Add working statement reduction | Yann Herklotz | 2019-05-12 | 2 | -30/+145 | |
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| * | Implement module item reduction properly | Yann Herklotz | 2019-05-11 | 4 | -12/+24 | |
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| * | Fix warnings for CI | Yann Herklotz | 2019-05-11 | 2 | -5/+4 | |
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| * | Add reduction unit tests | Yann Herklotz | 2019-05-11 | 1 | -0/+2 | |
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| * | Add Plate instance to Statement | Yann Herklotz | 2019-05-11 | 1 | -0/+6 | |
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| * | Add Mutation class in Mutate.hs | Yann Herklotz | 2019-05-11 | 1 | -1/+99 | |
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| * | Add Quote export to main module | Yann Herklotz | 2019-05-11 | 1 | -0/+3 | |
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| * | Add new reduction techniques | Yann Herklotz | 2019-05-11 | 2 | -153/+232 | |
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| * | Fixed parser to parse all the generated verilog | Yann Herklotz | 2019-05-10 | 3 | -29/+129 | |
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| * | Add always and initial blocks to parser | Yann Herklotz | 2019-05-10 | 3 | -8/+157 | |
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| * | Fix some of the doctests in Mutate.hs | Yann Herklotz | 2019-05-10 | 1 | -5/+5 | |
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| * | Add constant expression to expression conversion and vice versa | Yann Herklotz | 2019-05-10 | 2 | -0/+23 | |
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| * | Fix but remove the doctests for now | Yann Herklotz | 2019-05-10 | 2 | -36/+38 | |
| | | | | | | They were not working well with the current printing method. I have to find a way to remove the spaces from the output. | |||||
| * | Add parser and reducer tests | Yann Herklotz | 2019-05-09 | 2 | -0/+106 | |
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| * | Add new pretty printer with indentation | Yann Herklotz | 2019-05-09 | 9 | -219/+191 | |
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| * | Add reduction strategy for modules | Yann Herklotz | 2019-05-09 | 5 | -16/+166 | |
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| * | Add NFData to force evaluation of config file | Yann Herklotz | 2019-05-09 | 10 | -167/+102 | |
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| * | Upgrade stack LTS version | Yann Herklotz | 2019-05-09 | 1 | -3/+3 | |
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| * | Add supported simulators to readme | Yann Herklotz | 2019-05-09 | 1 | -0/+2 | |
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| * | Fix unusable UNPACK | Yann Herklotz | 2019-05-09 | 1 | -1/+1 | |
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| * | Add combinational and sequential logic support | Yann Herklotz | 2019-05-09 | 3 | -97/+55 | |
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| * | Only show the seed | Yann Herklotz | 2019-05-07 | 1 | -3/+1 | |
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| * | Add configuration options for all simulators | Yann Herklotz | 2019-05-07 | 7 | -66/+213 | |
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| * | Add description field to Yosys | Yann Herklotz | 2019-05-07 | 3 | -14/+13 | |
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| * | Use abc for verification | Yann Herklotz | 2019-05-07 | 3 | -8/+6 | |
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| * | Create better command line output | Yann Herklotz | 2019-05-07 | 3 | -9/+16 | |
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| * | Rename some functions to use nicer names | Yann Herklotz | 2019-05-07 | 10 | -55/+62 | |
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| * | Add support for multiple modules | Yann Herklotz | 2019-05-07 | 4 | -11/+41 | |
| | | | | | | | | Had to manually change module names, as Yosys does not change the module name at instantiation. This is done using sed. | |||||
| * | Fix a warning in cells_cyclone_v.v | Yann Herklotz | 2019-05-06 | 1 | -241/+241 | |
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| * | Fix bug in Config.hs | Yann Herklotz | 2019-05-06 | 1 | -6/+6 | |
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| * | Replace by the unisims model | Yann Herklotz | 2019-05-06 | 1 | -13/+7 | |
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| * | [Fix #49] Add LDPE cell to xilinx | Yann Herklotz | 2019-05-06 | 1 | -24/+39 | |
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| * | Support multiple reg assigns in if statements | Yann Herklotz | 2019-05-06 | 10 | -82/+110 | |
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| * | Modify generation of statements to create more interesting ones | Yann Herklotz | 2019-05-05 | 1 | -16/+35 | |
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| * | Format with brittany | Yann Herklotz | 2019-05-05 | 7 | -58/+91 | |
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| * | Write config file with seed to the fuzz directory | Yann Herklotz | 2019-05-05 | 2 | -18/+21 | |
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| * | Add seeds for reproducible runs | Yann Herklotz | 2019-05-05 | 5 | -46/+85 | |
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| * | Add more reduction to tests | Yann Herklotz | 2019-04-29 | 1 | -2/+10 | |
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| * | Add random bit selection for wires | Yann Herklotz | 2019-04-26 | 6 | -44/+89 | |
| | | | | | This has not been tested fully yet | |||||
| * | Add --num command line option | Yann Herklotz | 2019-04-25 | 1 | -2/+11 | |
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| * | Add time and date by default | Yann Herklotz | 2019-04-24 | 2 | -7/+20 | |
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| * | Add documentation to Config.hs | Yann Herklotz | 2019-04-23 | 2 | -18/+130 | |
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| * | Fix cells_xilinx_7.v LD and FD modules | Yann Herklotz | 2019-04-23 | 1 | -17/+0 | |
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| * | Fix some errors in the templates | Yann Herklotz | 2019-04-23 | 2 | -0/+53 | |
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index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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