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* Add output information to TypeYann Herklotz2019-04-188-82/+95
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* Add output path to each simulatorYann Herklotz2019-04-186-50/+121
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* Use new fuzzing technique instead of the old functionYann Herklotz2019-04-175-28/+36
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* Reduce the wire size as Quartus was crashingYann Herklotz2019-04-171-1/+9
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* Extend property tests to ResultTYann Herklotz2019-04-171-25/+21
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* Remove -Wall and -Werror, instead use --pedanticYann Herklotz2019-04-171-4/+1
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* Add new Fuzzing technique, that checks simulators against each otherYann Herklotz2019-04-171-11/+97
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* Add Show instances to simulatorsYann Herklotz2019-04-175-8/+25
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* Add '--pedantic' to travisYann Herklotz2019-04-171-3/+3
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* Fix tests and remove Parser tests for nowYann Herklotz2019-04-174-11/+65
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* Fix other type errors and replace with Result typeYann Herklotz2019-04-173-35/+49
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* Update simulator with Result typeYann Herklotz2019-04-175-61/+111
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* Add Fuzzer and implement it with the result typeYann Herklotz2019-04-171-35/+26
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* Move Reduce fileYann Herklotz2019-04-171-2/+2
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* Add Result typeYann Herklotz2019-04-171-0/+101
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* Move declaration of SourceInfoYann Herklotz2019-04-1513-37/+41
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* Format with brittany and add right modulesYann Herklotz2019-04-155-19/+20
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* Remove non existant exportsYann Herklotz2019-04-151-6/+1
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* Fix warningsYann Herklotz2019-04-151-9/+14
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* Rename Synthesisor -> SynthesiserYann Herklotz2019-04-155-13/+13
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* Replace Env by FuzzYann Herklotz2019-04-152-58/+113
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* Some changes to recursion schemesYann Herklotz2019-04-141-18/+4
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* Remove blocking assignment from GenerationYann Herklotz2019-04-141-1/+1
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* Change port declarations in ReduceYann Herklotz2019-04-141-4/+4
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* Print out local timeYann Herklotz2019-04-141-2/+5
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* Add bit vector to Icarus simulationYann Herklotz2019-04-141-1/+6
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* Add Bit vector instead of using numbersYann Herklotz2019-04-146-184/+142
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* Changes to general typesYann Herklotz2019-04-144-99/+90
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* Update property testsYann Herklotz2019-04-141-18/+17
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* Update cabal with added modulesYann Herklotz2019-04-141-0/+6
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* Add Eval module to evaluate expressionsYann Herklotz2019-04-141-0/+103
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* Add BitVec type to model Verilog bit vectorsYann Herklotz2019-04-141-0/+115
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* Add Quartus implementationYann Herklotz2019-04-141-0/+52
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* Merge branch 'docs'Yann Herklotz2019-04-132-0/+12
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| * Add partial documentationYann Herklotz2019-04-072-0/+12
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* | Fix tests passingYann Herklotz2019-04-133-8/+6
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* | Add recursion schemes implementationYann Herklotz2019-04-131-0/+84
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* | Remove Arbitrary modelYann Herklotz2019-04-122-227/+0
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* | Add for loop to designYann Herklotz2019-04-124-46/+135
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* | Change Port type to include lower boundYann Herklotz2019-04-126-25/+24
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* | Fix the setup script for awsYann Herklotz2019-04-121-3/+3
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* | Add vivado bugsYann Herklotz2019-04-125-0/+612
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* | Fix the generation of modules and add initialisationYann Herklotz2019-04-1015-256/+351
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* | Add probabilities to generation of expressionsYann Herklotz2019-04-097-37/+51
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* | Add generation of parameters and constant expressionsYann Herklotz2019-04-093-22/+60
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* | Add more configuration optionsYann Herklotz2019-04-091-31/+125
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* | Add Parameter type and remove DescriptionYann Herklotz2019-04-0915-95/+204
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* | Create Arbitrary moduleYann Herklotz2019-04-086-213/+235
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* Generate flip-flops instead of latchesYann Herklotz2019-04-063-14/+5
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* Fix setup script by mounting right driveYann Herklotz2019-04-061-1/+1
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