| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Add another example for declarations in verilog | Yann Herklotz | 2018-12-27 | 1 | -0/+31 |
| * | Add yosys shell script | Yann Herklotz | 2018-12-27 | 2 | -2/+32 |
| * | Generate completely random verilog | Yann Herklotz | 2018-12-27 | 1 | -3/+5 |
| * | Format fixes | Yann Herklotz | 2018-12-27 | 1 | -20/+20 |
| * | Small style change | Yann Herklotz | 2018-12-27 | 1 | -1/+1 |
| * | Improve expression and statement generation | Yann Herklotz | 2018-12-27 | 1 | -20/+96 |
| * | Fix tests with new changes | Yann Herklotz | 2018-12-27 | 1 | -1/+1 |
| * | Fix main and improve speed of run script | Yann Herklotz | 2018-12-25 | 2 | -2/+3 |
| * | Add documentation to main module | Yann Herklotz | 2018-12-25 | 1 | -0/+13 |
| * | Add code generation for new types | Yann Herklotz | 2018-12-25 | 1 | -20/+130 |
| * | Type fixes | Yann Herklotz | 2018-12-25 | 1 | -7/+8 |
| * | Rename Node to Int | Yann Herklotz | 2018-12-25 | 1 | -1/+1 |
| * | [Close #10, Fix #12] Add Mutations for wires | Yann Herklotz | 2018-12-25 | 1 | -7/+13 |
| * | Add more types | Yann Herklotz | 2018-12-25 | 1 | -41/+181 |
| * | Fix tests with ContAssign | Yann Herklotz | 2018-12-25 | 1 | -1/+1 |
| * | Add Helpers.hs | Yann Herklotz | 2018-12-25 | 2 | -0/+76 |
| * | Fix nesting, generation broken for nested groups | Yann Herklotz | 2018-12-23 | 1 | -3/+17 |
| * | Add nesting to the SourceText | Yann Herklotz | 2018-12-23 | 2 | -2/+19 |
| * | Add unit tests for the traversal | Yann Herklotz | 2018-12-23 | 4 | -8/+48 |
| * | [Fix #11] Implement the traversal | Yann Herklotz | 2018-12-23 | 1 | -18/+32 |
| * | Start implementing the nesting functionality | Yann Herklotz | 2018-12-23 | 1 | -2/+23 |
| * | Fix running the simulation | Yann Herklotz | 2018-12-23 | 1 | -1/+3 |
| * | Derive `Eq` for the Verilog AST. | Yann Herklotz | 2018-12-22 | 2 | -13/+14 |
| * | Add unimplemented nestId function | Yann Herklotz | 2018-12-22 | 1 | -0/+4 |
| * | Add Mutate module to VeriFuzz | Yann Herklotz | 2018-12-22 | 3 | -0/+18 |
| * | Format ASTGen | Yann Herklotz | 2018-12-22 | 1 | -6/+3 |
| * | [Fix #2] Add generation of AST from Circuit | Yann Herklotz | 2018-12-22 | 4 | -19/+33 |
| * | Add shared code to code generation | Yann Herklotz | 2018-12-22 | 2 | -0/+35 |
| * | Add more functions to the code generation | Yann Herklotz | 2018-12-22 | 2 | -25/+21 |
| * | Add more AST generation | Yann Herklotz | 2018-12-20 | 1 | -1/+19 |
| * | Fix documentation | Yann Herklotz | 2018-12-15 | 5 | -15/+117 |
| * | Add new imports | Yann Herklotz | 2018-12-15 | 1 | -3/+5 |
| * | Fix run_sim.sh | Yann Herklotz | 2018-12-15 | 1 | -2/+2 |
| * | Add AST generation to cabal | Yann Herklotz | 2018-12-15 | 1 | -3/+4 |
| * | Add AST generation | Yann Herklotz | 2018-12-15 | 1 | -0/+47 |
| * | Add qualified imports | Yann Herklotz | 2018-12-15 | 1 | -13/+12 |
| * | Rename types to circuit | Yann Herklotz | 2018-12-15 | 1 | -1/+15 |
| * | Add rerun script | Yann Herklotz | 2018-12-04 | 1 | -0/+7 |
| * | [Fix #1] Fix the negative number generation | Yann Herklotz | 2018-12-04 | 2 | -2/+5 |
| * | Add newline to test | Yann Herklotz | 2018-12-04 | 1 | -0/+1 |
| * | Add quickcheck to main | Yann Herklotz | 2018-12-04 | 2 | -0/+4 |
| * | [Fix #8] Add Circuit newtype | Yann Herklotz | 2018-12-02 | 1 | -0/+3 |
| * | Fix typo | Yann Herklotz | 2018-12-01 | 1 | -1/+1 |
| * | Add newline after module declaration | Yann Herklotz | 2018-12-01 | 1 | -1/+1 |
| * | Fix the code generation | Yann Herklotz | 2018-12-01 | 1 | -1/+13 |
| * | Add all arbitrary instances and fix identifier | Yann Herklotz | 2018-12-01 | 1 | -15/+65 |
| * | Add more code to the shared code | Yann Herklotz | 2018-12-01 | 2 | -15/+15 |
| * | Add modport helper function | Yann Herklotz | 2018-12-01 | 1 | -0/+3 |
| * | Add more code generation for expressions | Yann Herklotz | 2018-12-01 | 1 | -0/+40 |
| * | Add missing modules to main library | Yann Herklotz | 2018-12-01 | 1 | -0/+2 |
 |
index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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