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* | Format and remove unnecessary declarations | Yann Herklotz | 2018-11-16 | 1 | -6/+3 | |
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* | Add statements to the Verilog module | Yann Herklotz | 2018-11-16 | 1 | -12/+24 | |
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* | Better format for the Verilog file | Yann Herklotz | 2018-11-16 | 1 | -6/+6 | |
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* | Add style to the files | Yann Herklotz | 2018-11-14 | 7 | -26/+25 | |
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* | Add testbench to the end | Yann Herklotz | 2018-11-09 | 1 | -1/+1 | |
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* | Generate some Verilog code from graph | Yann Herklotz | 2018-11-09 | 2 | -9/+38 | |
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* | Random generation of DAG | Yann Herklotz | 2018-11-09 | 4 | -34/+46 | |
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* | Improve cabal module | Yann Herklotz | 2018-11-09 | 1 | -1/+19 | |
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* | Add main module | Yann Herklotz | 2018-11-09 | 1 | -0/+13 | |
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* | Add initial module files | Yann Herklotz | 2018-11-09 | 3 | -0/+22 | |
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* | Removing report | Yann Herklotz | 2018-11-08 | 2 | -153/+0 | |
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* | Rename folder to examples | Yann Herklotz | 2018-11-08 | 1 | -0/+0 | |
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* | Add simple verilog AND gate | Yann Herklotz | 2018-11-07 | 2 | -1/+24 | |
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* | Generate random undirected graph | Yann Herklotz | 2018-11-05 | 3 | -30/+25 | |
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* | Add references | Yann Herklotz | 2018-11-05 | 2 | -0/+153 | |
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* | Simple visualization | Yann Herklotz | 2018-10-29 | 1 | -18/+7 | |
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* | Add case to make it more readable | Yann Herklotz | 2018-10-29 | 1 | -5/+10 | |
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* | Partial tree visualization | Yann Herklotz | 2018-10-29 | 1 | -1/+2 | |
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* | Broken change rendering the graph | Yann Herklotz | 2018-10-29 | 2 | -2/+19 | |
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* | Random generation of trees | Yann Herklotz | 2018-10-28 | 1 | -8/+18 | |
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* | Initial commit | Yann Herklotz | 2018-10-28 | 5 | -0/+85 | |
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* | Initial commit | Yann Herklotz | 2018-10-23 | 1 | -0/+2 | |