verismith - Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.

	Commit message (Collapse)	Author	Age	Files	Lines
*	Add back fixed doctest	Yann Herklotz	2019-04-01	3	-4/+34
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*	Fix warnings in code	Yann Herklotz	2019-03-31	3	-26/+8
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*	Remove doctest temporarily	Yann Herklotz	2019-03-31	1	-13/+0
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*	Fix some of the tests	Yann Herklotz	2019-03-31	3	-3/+6
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*	Rewrite the parser with real lexer	Yann Herklotz	2019-03-31	9	-581/+977
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*	Add documentation	Yann Herklotz	2019-03-30	1	-10/+28
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*	Add if statement type	Yann Herklotz	2019-03-30	1	-0/+4
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*	Useful renames and add if statement generation	Yann Herklotz	2019-03-30	1	-141/+143
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*	Add some documentation	Yann Herklotz	2019-03-30	1	-9/+14
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*	Change license name	Yann Herklotz	2019-03-30	25	-29/+27
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*	Move the analysed bugs to better file names	Yann Herklotz Grave	2019-03-16	5	-0/+2
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*	Add more examples to config file	Yann Herklotz Grave	2019-03-16	1	-1/+2
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*	Add scripts	Yann Herklotz Grave	2019-03-16	1	-0/+20
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*	Add more options to main app	Yann Herklotz Grave	2019-03-07	2	-16/+24
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*	Fix build	Yann Herklotz Grave	2019-03-07	1	-11/+0
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*	Add proper register generation	Yann Herklotz Grave	2019-03-07	2	-15/+17
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*	Fix build errors and simplify names	Yann Herklotz Grave	2019-03-06	1	-33/+42
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*	Add last bug that was found	Yann Herklotz Grave	2019-03-06	2	-0/+210
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*	Add always blocks to the main generation	Yann Herklotz Grave	2019-03-06	1	-7/+44
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*	Add more probabilities to config	Yann Herklotz Grave	2019-03-06	3	-26/+33
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*	Rename Stmnt to Statement	Yann Herklotz Grave	2019-03-06	3	-37/+37
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*	Hlint suggestions	Yann Herklotz Grave	2019-03-06	1	-4/+4
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*	Fix positive arbitrary generation	Yann Herklotz Grave	2019-03-06	1	-1/+1
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*	Add more configuration options	Yann Herklotz Grave	2019-03-06	2	-7/+57
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*	Add example config file	Yann Herklotz Grave	2019-03-04	1	-0/+4
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*	Run formatting on Config.hs	Yann Herklotz Grave	2019-03-04	1	-6/+12
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*	Create procedural generation for Verilog	Yann Herklotz Grave	2019-03-04	1	-12/+3
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*	Add toml configuration support for probabilities	Yann Herklotz Grave	2019-03-04	2	-0/+59
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*	Clean imports	Yann Herklotz Grave	2019-03-04	1	-1/+2
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*	Fix all the warnings and fix building	Yann Herklotz Grave	2019-03-03	1	-10/+15
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*	Add transformers and procedural generation	Yann Herklotz Grave	2019-03-03	5	-25/+102
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*	Add more bugs	Yann Herklotz Grave	2019-03-03	4	-0/+420
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*	Add data to .gitattributes	Yann Herklotz Grave	2019-03-03	1	-0/+1
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*	Add .gitAttributes	Yann Herklotz Grave	2019-03-03	2	-1/+2
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*	Add found bugs	Yann Herklotz Grave	2019-03-03	9	-0/+847
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*	Add applicative instance and Expr reduction	Yann Herklotz Grave	2019-03-02	1	-20/+48
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*	Some formatting	Yann Herklotz Grave	2019-03-01	1	-4/+4
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*	Remove warn in cabal	Yann Herklotz Grave	2019-03-01	1	-1/+1
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*	Add better reduction with custom type	Yann Herklotz Grave	2019-03-01	1	-48/+73
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*	Add lens to access main module in SourceInfo	Yann Herklotz Grave	2019-03-01	3	-7/+23
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*	Lint fix	Yann Herklotz Grave	2019-03-01	1	-1/+1
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*	[Fix #35] Add reducer that tries and reduce Verilog given a run	Yann Herklotz Grave	2019-03-01	1	-24/+94
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*	[Fix #38] Fix parser to correctly identify input and output ports	Yann Herklotz Grave	2019-03-01	1	-2/+13
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*	Add general function to mutations	Yann Herklotz Grave	2019-03-01	1	-1/+7
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*	[Fix #37] Fix types in the simulator with more general functions	Yann Herklotz Grave	2019-03-01	3	-55/+63
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*	Add missing modules to cabal	Yann Herklotz Grave	2019-03-01	1	-9/+9
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*	Add missing modules to Internal module	Yann Herklotz Grave	2019-03-01	1	-1/+3
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*	Add Simulation and Synthesis environments	Yann Herklotz Grave	2019-03-01	1	-12/+31
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*	Fix indentation	Yann Herklotz Grave	2019-03-01	1	-19/+22
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*	Fix warnings in ASTGen and make it more general	Yann Herklotz Grave	2019-03-01	1	-11/+9
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