| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Add dired locals to open verilog files | Yann Herklotz | 2019-04-06 | 1 | -0/+1 |
| * | New combine function | Yann Herklotz | 2019-04-04 | 1 | -0/+5 |
| * | Fix adding port to state and add everything to output | Yann Herklotz | 2019-04-04 | 1 | -8/+20 |
| * | Better formatting for if-statement | Yann Herklotz | 2019-04-04 | 1 | -2/+2 |
| * | Reorganise runEquivalence | Yann Herklotz | 2019-04-04 | 1 | -5/+10 |
| * | Fix for latches in design | Yann Herklotz | 2019-04-04 | 1 | -0/+1 |
| * | Add config command and more fuzz options | Yann Herklotz | 2019-04-04 | 1 | -8/+57 |
| * | Add verilog modules to equivalence checking | Yann Herklotz | 2019-04-03 | 1 | -1/+1 |
| * | Fix infinite loop in state based generation | Yann Herklotz | 2019-04-03 | 2 | -13/+18 |
| * | Generate Verilog instead of ModDecl | Yann Herklotz | 2019-04-03 | 3 | -4/+3 |
| * | Add missing modules when using always blocks | Yann Herklotz | 2019-04-03 | 2 | -75/+108 |
| * | Add quick fix to run without dsp48 | Yann Herklotz | 2019-04-03 | 2 | -2/+3 |
| * | Export Vivado types and fix test failure | Yann Herklotz | 2019-04-03 | 3 | -6/+10 |
| * | Apply brittany to modified modules | Yann Herklotz | 2019-04-03 | 2 | -12/+19 |
| * | Add Vivado module | Yann Herklotz | 2019-04-03 | 3 | -0/+61 |
| * | Fix to the logger | Yann Herklotz | 2019-04-03 | 5 | -14/+23 |
| * | Formatting file | Yann Herklotz | 2019-04-03 | 1 | -92/+92 |
| * | Add emacs mode line to Lex.x | Yann Herklotz | 2019-04-02 | 1 | -0/+1 |
| * | Large refactor with passing tests | Yann Herklotz | 2019-04-02 | 28 | -283/+533 |
| * | Rename to Verilog | Yann Herklotz | 2019-04-02 | 12 | -40/+42 |
| * | Fix hlint hints | Yann Herklotz | 2019-04-02 | 3 | -9/+10 |
| * | Add more configuration options and small fix | Yann Herklotz | 2019-04-02 | 3 | -21/+40 |
| * | Remove Hedgehog from modulev0.2.0.0 | Yann Herklotz | 2019-04-02 | 1 | -8/+6 |
| * | Add conditionals to config | Yann Herklotz | 2019-04-02 | 1 | -1/+5 |
| * | Make GenVerilog part of Arb | Yann Herklotz | 2019-04-02 | 1 | -3/+2 |
| * | Fix Circuit types | Yann Herklotz | 2019-04-02 | 1 | -5/+4 |
| * | Switch all the types from Arbitrary to Arb | Yann Herklotz | 2019-04-02 | 1 | -208/+223 |
| * | Switch to Hedgehog in graph and verilog generation | Yann Herklotz | 2019-04-02 | 2 | -39/+39 |
| * | Fix random generation for Circuit | Yann Herklotz | 2019-04-02 | 1 | -19/+29 |
| * | Remove fgl-arbitrary completely | Yann Herklotz | 2019-04-02 | 3 | -27/+0 |
| * | Change property tests to use Hedgehog | Yann Herklotz | 2019-04-02 | 1 | -46/+32 |
| * | Remove QuickCheck and use Hedgehog instead | Yann Herklotz | 2019-04-02 | 3 | -19/+10 |
| * | Small fix to indentation | Yann Herklotz | 2019-04-01 | 1 | -4/+4 |
| * | Run through brittany | Yann Herklotz | 2019-04-01 | 9 | -214/+234 |
| * | Add back fixed doctest | Yann Herklotz | 2019-04-01 | 3 | -4/+34 |
| * | Fix warnings in code | Yann Herklotz | 2019-03-31 | 3 | -26/+8 |
| * | Remove doctest temporarily | Yann Herklotz | 2019-03-31 | 1 | -13/+0 |
| * | Fix some of the tests | Yann Herklotz | 2019-03-31 | 3 | -3/+6 |
| * | Rewrite the parser with real lexer | Yann Herklotz | 2019-03-31 | 9 | -581/+977 |
| * | Add documentation | Yann Herklotz | 2019-03-30 | 1 | -10/+28 |
| * | Add if statement type | Yann Herklotz | 2019-03-30 | 1 | -0/+4 |
| * | Useful renames and add if statement generation | Yann Herklotz | 2019-03-30 | 1 | -141/+143 |
| * | Add some documentation | Yann Herklotz | 2019-03-30 | 1 | -9/+14 |
| * | Change license name | Yann Herklotz | 2019-03-30 | 25 | -29/+27 |
| * | Move the analysed bugs to better file names | Yann Herklotz Grave | 2019-03-16 | 5 | -0/+2 |
| * | Add more examples to config file | Yann Herklotz Grave | 2019-03-16 | 1 | -1/+2 |
| * | Add scripts | Yann Herklotz Grave | 2019-03-16 | 1 | -0/+20 |
| * | Add more options to main app | Yann Herklotz Grave | 2019-03-07 | 2 | -16/+24 |
| * | Fix build | Yann Herklotz Grave | 2019-03-07 | 1 | -11/+0 |
| * | Add proper register generation | Yann Herklotz Grave | 2019-03-07 | 2 | -15/+17 |
 |
index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
| aboutsummaryrefslogtreecommitdiffstats |