| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | [Fix #8] Add Circuit newtype | Yann Herklotz | 2018-12-02 | 1 | -0/+3 | |
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| * | Fix typo | Yann Herklotz | 2018-12-01 | 1 | -1/+1 | |
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| * | Add newline after module declaration | Yann Herklotz | 2018-12-01 | 1 | -1/+1 | |
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| * | Fix the code generation | Yann Herklotz | 2018-12-01 | 1 | -1/+13 | |
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| * | Add all arbitrary instances and fix identifier | Yann Herklotz | 2018-12-01 | 1 | -15/+65 | |
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| * | Add more code to the shared code | Yann Herklotz | 2018-12-01 | 2 | -15/+15 | |
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| * | Add modport helper function | Yann Herklotz | 2018-12-01 | 1 | -0/+3 | |
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| * | Add more code generation for expressions | Yann Herklotz | 2018-12-01 | 1 | -0/+40 | |
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| * | Add missing modules to main library | Yann Herklotz | 2018-12-01 | 1 | -0/+2 | |
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| * | Add internal shared module | Yann Herklotz | 2018-12-01 | 1 | -0/+4 | |
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| * | Move generation to new location | Yann Herklotz | 2018-12-01 | 2 | -59/+79 | |
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| * | [lint] Remove unnecessary '$' | Yann Herklotz | 2018-12-01 | 1 | -1/+1 | |
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| * | Fix data types and apply more hlint suggestions | Yann Herklotz | 2018-12-01 | 1 | -8/+6 | |
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| * | Add new modules | Yann Herklotz | 2018-12-01 | 1 | -1/+3 | |
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| * | Apply HLint rules | Yann Herklotz | 2018-12-01 | 1 | -1/+1 | |
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| * | Add helper methods | Yann Herklotz | 2018-12-01 | 1 | -6/+15 | |
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| * | Add assignment to ModuleItem | Yann Herklotz | 2018-11-30 | 1 | -3/+2 | |
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| * | Add more types | Yann Herklotz | 2018-11-30 | 1 | -12/+25 | |
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| * | Make the test case clearer | Yann Herklotz | 2018-11-30 | 1 | -3/+4 | |
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| * | Add tests to the cabal file | Yann Herklotz | 2018-11-30 | 1 | -0/+3 | |
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| * | Fix type issue in main | Yann Herklotz | 2018-11-30 | 2 | -6/+11 | |
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| * | Add first property test | Yann Herklotz | 2018-11-30 | 3 | -12/+36 | |
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| * | Make simple test pass | Yann Herklotz | 2018-11-30 | 1 | -1/+1 | |
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| * | Rename the Test file | Yann Herklotz | 2018-11-30 | 2 | -1/+1 | |
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| * | Reformat the main file and upgrade lts | Yann Herklotz | 2018-11-30 | 3 | -14/+15 | |
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| * | Restructure and add tests | Yann Herklotz | 2018-11-30 | 3 | -9/+34 | |
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| * | Add lens library and extend types for AST | Yann Herklotz | 2018-11-30 | 2 | -8/+67 | |
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| * | Add AST to the exported modules | Yann Herklotz | 2018-11-30 | 1 | -0/+3 | |
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| * | Add some simplifications (map -> fmap) | Yann Herklotz | 2018-11-29 | 1 | -5/+6 | |
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| * | Add Verilog AST | Yann Herklotz | 2018-11-29 | 1 | -0/+13 | |
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| * | Improve generation | Yann Herklotz | 2018-11-16 | 1 | -15/+15 | |
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| * | Basic generation with errors | Yann Herklotz | 2018-11-16 | 3 | -6/+24 | |
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| * | Add .gitignore | Yann Herklotz | 2018-11-16 | 1 | -0/+5 | |
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| * | Remove Nor and Nand from types | Yann Herklotz | 2018-11-16 | 1 | -4/+2 | |
| | | | | | Should add Not to the list, as that will emulate those fine. | |||||
| * | Format and remove unnecessary declarations | Yann Herklotz | 2018-11-16 | 1 | -6/+3 | |
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| * | Add statements to the Verilog module | Yann Herklotz | 2018-11-16 | 1 | -12/+24 | |
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| * | Better format for the Verilog file | Yann Herklotz | 2018-11-16 | 1 | -6/+6 | |
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| * | Add style to the files | Yann Herklotz | 2018-11-14 | 7 | -26/+25 | |
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| * | Add testbench to the end | Yann Herklotz | 2018-11-09 | 1 | -1/+1 | |
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| * | Generate some Verilog code from graph | Yann Herklotz | 2018-11-09 | 2 | -9/+38 | |
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| * | Random generation of DAG | Yann Herklotz | 2018-11-09 | 4 | -34/+46 | |
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| * | Improve cabal module | Yann Herklotz | 2018-11-09 | 1 | -1/+19 | |
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| * | Add main module | Yann Herklotz | 2018-11-09 | 1 | -0/+13 | |
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| * | Add initial module files | Yann Herklotz | 2018-11-09 | 3 | -0/+22 | |
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| * | Removing report | Yann Herklotz | 2018-11-08 | 2 | -153/+0 | |
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| * | Rename folder to examples | Yann Herklotz | 2018-11-08 | 1 | -0/+0 | |
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| * | Add simple verilog AND gate | Yann Herklotz | 2018-11-07 | 2 | -1/+24 | |
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| * | Generate random undirected graph | Yann Herklotz | 2018-11-05 | 3 | -30/+25 | |
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| * | Add references | Yann Herklotz | 2018-11-05 | 2 | -0/+153 | |
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| * | Simple visualization | Yann Herklotz | 2018-10-29 | 1 | -18/+7 | |
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index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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