verismith - Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.

	Commit message (Collapse)	Author	Age	Files	Lines
*	Another fix to copyright	Yann Herklotz	2018-12-28	1	-1/+1
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*	Fix copyright notice	Yann Herklotz	2018-12-28	1	-1/+1
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*	Add simulator module	Yann Herklotz	2018-12-28	5	-0/+215
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*	Fix imports and cabal file	Yann Herklotz	2018-12-28	5	-24/+29
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*	Move verilog files into specific module	Yann Herklotz	2018-12-28	4	-21/+104
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*	Add executable for Yosys	Yann Herklotz	2018-12-28	1	-0/+1
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*	Edit main	Yann Herklotz	2018-12-28	1	-3/+3
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*	Add instantiation function	Yann Herklotz	2018-12-27	1	-2/+7
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*	Remove OverloadedStrings in favour of declaration in module	Yann Herklotz	2018-12-27	7	-14/+1
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*	Add another example for declarations in verilog	Yann Herklotz	2018-12-27	1	-0/+31
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*	Add yosys shell script	Yann Herklotz	2018-12-27	2	-2/+32
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*	Generate completely random verilog	Yann Herklotz	2018-12-27	1	-3/+5
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*	Format fixes	Yann Herklotz	2018-12-27	1	-20/+20
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*	Small style change	Yann Herklotz	2018-12-27	1	-1/+1
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*	Improve expression and statement generation	Yann Herklotz	2018-12-27	1	-20/+96
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*	Fix tests with new changes	Yann Herklotz	2018-12-27	1	-1/+1
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*	Fix main and improve speed of run script	Yann Herklotz	2018-12-25	2	-2/+3
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*	Add documentation to main module	Yann Herklotz	2018-12-25	1	-0/+13
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*	Add code generation for new types	Yann Herklotz	2018-12-25	1	-20/+130
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*	Type fixes	Yann Herklotz	2018-12-25	1	-7/+8
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*	Rename Node to Int	Yann Herklotz	2018-12-25	1	-1/+1
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*	[Close #10, Fix #12] Add Mutations for wires	Yann Herklotz	2018-12-25	1	-7/+13
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*	Add more types	Yann Herklotz	2018-12-25	1	-41/+181
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*	Fix tests with ContAssign	Yann Herklotz	2018-12-25	1	-1/+1
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*	Add Helpers.hs	Yann Herklotz	2018-12-25	2	-0/+76
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*	Fix nesting, generation broken for nested groups	Yann Herklotz	2018-12-23	1	-3/+17
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*	Add nesting to the SourceText	Yann Herklotz	2018-12-23	2	-2/+19
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*	Add unit tests for the traversal	Yann Herklotz	2018-12-23	4	-8/+48
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*	[Fix #11] Implement the traversal	Yann Herklotz	2018-12-23	1	-18/+32
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*	Start implementing the nesting functionality	Yann Herklotz	2018-12-23	1	-2/+23
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*	Fix running the simulation	Yann Herklotz	2018-12-23	1	-1/+3
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*	Derive `Eq` for the Verilog AST.	Yann Herklotz	2018-12-22	2	-13/+14
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*	Add unimplemented nestId function	Yann Herklotz	2018-12-22	1	-0/+4
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*	Add Mutate module to VeriFuzz	Yann Herklotz	2018-12-22	3	-0/+18
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*	Format ASTGen	Yann Herklotz	2018-12-22	1	-6/+3
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*	[Fix #2] Add generation of AST from Circuit	Yann Herklotz	2018-12-22	4	-19/+33
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*	Add shared code to code generation	Yann Herklotz	2018-12-22	2	-0/+35
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*	Add more functions to the code generation	Yann Herklotz	2018-12-22	2	-25/+21
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*	Add more AST generation	Yann Herklotz	2018-12-20	1	-1/+19
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*	Fix documentation	Yann Herklotz	2018-12-15	5	-15/+117
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*	Add new imports	Yann Herklotz	2018-12-15	1	-3/+5
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*	Fix run_sim.sh	Yann Herklotz	2018-12-15	1	-2/+2
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*	Add AST generation to cabal	Yann Herklotz	2018-12-15	1	-3/+4
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*	Add AST generation	Yann Herklotz	2018-12-15	1	-0/+47
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*	Add qualified imports	Yann Herklotz	2018-12-15	1	-13/+12
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*	Rename types to circuit	Yann Herklotz	2018-12-15	1	-1/+15
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*	Add rerun script	Yann Herklotz	2018-12-04	1	-0/+7
\| \| \| \|	This should be turned into Haskell though.
*	[Fix #1] Fix the negative number generation	Yann Herklotz	2018-12-04	2	-2/+5
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*	Add newline to test	Yann Herklotz	2018-12-04	1	-0/+1
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*	Add quickcheck to main	Yann Herklotz	2018-12-04	2	-0/+4
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