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* Add new modules to fix Quartus equivalence checkYann Herklotz2019-04-212-1/+55
* Add helper functions to execute fuzzing multiple timesYann Herklotz2019-04-192-11/+26
* Move --pedantic flag to the endYann Herklotz2019-04-191-1/+1
* Fix compiling on CIYann Herklotz2019-04-192-2/+7
* Fix some suggestions in Result.hsYann Herklotz2019-04-191-5/+2
* Equivalence test now runningYann Herklotz2019-04-191-2/+1
* Extend ResultT and Result with more instancesYann Herklotz2019-04-193-9/+49
* Add output information to TypeYann Herklotz2019-04-188-82/+95
* Add output path to each simulatorYann Herklotz2019-04-186-50/+121
* Use new fuzzing technique instead of the old functionYann Herklotz2019-04-175-28/+36
* Reduce the wire size as Quartus was crashingYann Herklotz2019-04-171-1/+9
* Extend property tests to ResultTYann Herklotz2019-04-171-25/+21
* Remove -Wall and -Werror, instead use --pedanticYann Herklotz2019-04-171-4/+1
* Add new Fuzzing technique, that checks simulators against each otherYann Herklotz2019-04-171-11/+97
* Add Show instances to simulatorsYann Herklotz2019-04-175-8/+25
* Add '--pedantic' to travisYann Herklotz2019-04-171-3/+3
* Fix tests and remove Parser tests for nowYann Herklotz2019-04-174-11/+65
* Fix other type errors and replace with Result typeYann Herklotz2019-04-173-35/+49
* Update simulator with Result typeYann Herklotz2019-04-175-61/+111
* Add Fuzzer and implement it with the result typeYann Herklotz2019-04-171-35/+26
* Move Reduce fileYann Herklotz2019-04-171-2/+2
* Add Result typeYann Herklotz2019-04-171-0/+101
* Move declaration of SourceInfoYann Herklotz2019-04-1513-37/+41
* Format with brittany and add right modulesYann Herklotz2019-04-155-19/+20
* Remove non existant exportsYann Herklotz2019-04-151-6/+1
* Fix warningsYann Herklotz2019-04-151-9/+14
* Rename Synthesisor -> SynthesiserYann Herklotz2019-04-155-13/+13
* Replace Env by FuzzYann Herklotz2019-04-152-58/+113
* Some changes to recursion schemesYann Herklotz2019-04-141-18/+4
* Remove blocking assignment from GenerationYann Herklotz2019-04-141-1/+1
* Change port declarations in ReduceYann Herklotz2019-04-141-4/+4
* Print out local timeYann Herklotz2019-04-141-2/+5
* Add bit vector to Icarus simulationYann Herklotz2019-04-141-1/+6
* Add Bit vector instead of using numbersYann Herklotz2019-04-146-184/+142
* Changes to general typesYann Herklotz2019-04-144-99/+90
* Update property testsYann Herklotz2019-04-141-18/+17
* Update cabal with added modulesYann Herklotz2019-04-141-0/+6
* Add Eval module to evaluate expressionsYann Herklotz2019-04-141-0/+103
* Add BitVec type to model Verilog bit vectorsYann Herklotz2019-04-141-0/+115
* Add Quartus implementationYann Herklotz2019-04-141-0/+52
* Merge branch 'docs'Yann Herklotz2019-04-132-0/+12
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| * Add partial documentationYann Herklotz2019-04-072-0/+12
* | Fix tests passingYann Herklotz2019-04-133-8/+6
* | Add recursion schemes implementationYann Herklotz2019-04-131-0/+84
* | Remove Arbitrary modelYann Herklotz2019-04-122-227/+0
* | Add for loop to designYann Herklotz2019-04-124-46/+135
* | Change Port type to include lower boundYann Herklotz2019-04-126-25/+24
* | Fix the setup script for awsYann Herklotz2019-04-121-3/+3
* | Add vivado bugsYann Herklotz2019-04-125-0/+612
* | Fix the generation of modules and add initialisationYann Herklotz2019-04-1015-256/+351