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* Move declaration of SourceInfoYann Herklotz2019-04-1513-37/+41
* Format with brittany and add right modulesYann Herklotz2019-04-155-19/+20
* Remove non existant exportsYann Herklotz2019-04-151-6/+1
* Fix warningsYann Herklotz2019-04-151-9/+14
* Rename Synthesisor -> SynthesiserYann Herklotz2019-04-155-13/+13
* Replace Env by FuzzYann Herklotz2019-04-152-58/+113
* Some changes to recursion schemesYann Herklotz2019-04-141-18/+4
* Remove blocking assignment from GenerationYann Herklotz2019-04-141-1/+1
* Change port declarations in ReduceYann Herklotz2019-04-141-4/+4
* Print out local timeYann Herklotz2019-04-141-2/+5
* Add bit vector to Icarus simulationYann Herklotz2019-04-141-1/+6
* Add Bit vector instead of using numbersYann Herklotz2019-04-146-184/+142
* Changes to general typesYann Herklotz2019-04-144-99/+90
* Update property testsYann Herklotz2019-04-141-18/+17
* Update cabal with added modulesYann Herklotz2019-04-141-0/+6
* Add Eval module to evaluate expressionsYann Herklotz2019-04-141-0/+103
* Add BitVec type to model Verilog bit vectorsYann Herklotz2019-04-141-0/+115
* Add Quartus implementationYann Herklotz2019-04-141-0/+52
* Merge branch 'docs'Yann Herklotz2019-04-132-0/+12
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| * Add partial documentationYann Herklotz2019-04-072-0/+12
* | Fix tests passingYann Herklotz2019-04-133-8/+6
* | Add recursion schemes implementationYann Herklotz2019-04-131-0/+84
* | Remove Arbitrary modelYann Herklotz2019-04-122-227/+0
* | Add for loop to designYann Herklotz2019-04-124-46/+135
* | Change Port type to include lower boundYann Herklotz2019-04-126-25/+24
* | Fix the setup script for awsYann Herklotz2019-04-121-3/+3
* | Add vivado bugsYann Herklotz2019-04-125-0/+612
* | Fix the generation of modules and add initialisationYann Herklotz2019-04-1015-256/+351
* | Add probabilities to generation of expressionsYann Herklotz2019-04-097-37/+51
* | Add generation of parameters and constant expressionsYann Herklotz2019-04-093-22/+60
* | Add more configuration optionsYann Herklotz2019-04-091-31/+125
* | Add Parameter type and remove DescriptionYann Herklotz2019-04-0915-95/+204
* | Create Arbitrary moduleYann Herklotz2019-04-086-213/+235
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* Generate flip-flops instead of latchesYann Herklotz2019-04-063-14/+5
* Fix setup script by mounting right driveYann Herklotz2019-04-061-1/+1
* Add more primitives to data/Yann Herklotz2019-04-062-7/+77
* Add dired locals to open verilog filesYann Herklotz2019-04-061-0/+1
* New combine functionYann Herklotz2019-04-041-0/+5
* Fix adding port to state and add everything to outputYann Herklotz2019-04-041-8/+20
* Better formatting for if-statementYann Herklotz2019-04-041-2/+2
* Reorganise runEquivalenceYann Herklotz2019-04-041-5/+10
* Fix for latches in designYann Herklotz2019-04-041-0/+1
* Add config command and more fuzz optionsYann Herklotz2019-04-041-8/+57
* Add verilog modules to equivalence checkingYann Herklotz2019-04-031-1/+1
* Fix infinite loop in state based generationYann Herklotz2019-04-032-13/+18
* Generate Verilog instead of ModDeclYann Herklotz2019-04-033-4/+3
* Add missing modules when using always blocksYann Herklotz2019-04-032-75/+108
* Add quick fix to run without dsp48Yann Herklotz2019-04-032-2/+3
* Export Vivado types and fix test failureYann Herklotz2019-04-033-6/+10
* Apply brittany to modified modulesYann Herklotz2019-04-032-12/+19