| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Fix all the compile and test errors | Yann Herklotz | 2019-02-01 | 14 | -62/+74 |
| * | Fix imports | Yann Herklotz | 2019-02-01 | 13 | -57/+61 |
| * | Fix modules in cabal file | Yann Herklotz | 2019-02-01 | 1 | -18/+16 |
| * | Rename XST and add imports | Yann Herklotz | 2019-02-01 | 2 | -20/+32 |
| * | Fix internal modules | Yann Herklotz | 2019-02-01 | 1 | -1/+11 |
| * | More restructuring | Yann Herklotz | 2019-02-01 | 15 | -130/+26 |
| * | Structure changes | Yann Herklotz | 2019-02-01 | 9 | -26/+65 |
| * | Reformat cabal file | Yann Herklotz | 2019-02-01 | 1 | -92/+93 |
| * | Add back Show for tests | Yann Herklotz | 2019-02-01 | 1 | -21/+21 |
| * | Add type annotations | Yann Herklotz | 2019-02-01 | 1 | -0/+2 |
| * | [Fix #28] Add Expression generation with context | Yann Herklotz | 2019-02-01 | 1 | -16/+29 |
| * | [Fix #27] Add function to Expr and add Generation type | Yann Herklotz | 2019-02-01 | 2 | -22/+54 |
| * | [Fix #24] Small changes and looked at always block output | Yann Herklotz | 2019-02-01 | 1 | -7/+9 |
| * | Make code a bit more readable | Yann Herklotz | 2019-02-01 | 1 | -1/+2 |
| * | Remove extra import | Yann Herklotz | 2019-02-01 | 1 | -1/+0 |
| * | Better formatting | Yann Herklotz | 2019-02-01 | 1 | -8/+17 |
| * | Add colon | Yann Herklotz | 2019-01-24 | 1 | -4/+4 |
| * | Add filepath dependencies | Yann Herklotz | 2019-01-23 | 1 | -0/+1 |
| * | Add echo do all the simulators | Yann Herklotz | 2019-01-23 | 3 | -0/+9 |
| * | Add better echo | Yann Herklotz | 2019-01-23 | 1 | -5/+14 |
| * | Better AST generation from DAG | Yann Herklotz | 2019-01-23 | 1 | -1/+4 |
| * | Fix the main app | Yann Herklotz | 2019-01-23 | 1 | -5/+6 |
| * | Add report | Yann Herklotz | 2019-01-23 | 1 | -0/+0 |
| * | Better multithreading | Yann Herklotz | 2019-01-22 | 5 | -13/+23 |
| * | Make where clause nicer | Yann Herklotz | 2019-01-22 | 1 | -2/+4 |
| * | Add shelly and equiv to gitignore | Yann Herklotz | 2019-01-21 | 1 | -0/+2 |
| * | Compile main as threaded | Yann Herklotz | 2019-01-21 | 1 | -0/+1 |
| * | Make main infinitely recurse | Yann Herklotz | 2019-01-21 | 1 | -10/+23 |
| * | [Fix #22] Fix SAT solver equivalence checking | Yann Herklotz | 2019-01-20 | 3 | -4/+40 |
| * | [Fix #26] Add support for SymbiYosys | Yann Herklotz | 2019-01-20 | 2 | -4/+10 |
| * | Format of main file | Yann Herklotz | 2019-01-20 | 1 | -4/+6 |
| * | Prettify files | Yann Herklotz | 2019-01-20 | 9 | -55/+117 |
| * | Add sby config | Yann Herklotz | 2019-01-20 | 1 | -5/+45 |
| * | Fix unit test and cabal file | Yann Herklotz | 2019-01-20 | 2 | -2/+1 |
| * | Add internal simulator module | Yann Herklotz | 2019-01-20 | 1 | -2/+3 |
| * | Add template file | Yann Herklotz | 2019-01-20 | 4 | -47/+72 |
| * | Rename moduleId to modId | Yann Herklotz | 2019-01-20 | 9 | -25/+39 |
| * | Reformat with stylish-haskell | Yann Herklotz | 2019-01-19 | 17 | -109/+90 |
| * | Add .hlint.yaml | Yann Herklotz | 2019-01-19 | 1 | -0/+60 |
| * | Add hlint changes | Yann Herklotz | 2019-01-19 | 3 | -4/+3 |
| * | Set column to 100 | Yann Herklotz | 2019-01-19 | 9 | -83/+31 |
| * | Add brittany formatting instead of stylish-haskell | Yann Herklotz | 2019-01-19 | 17 | -290/+387 |
| * | Small improvement to stmnt and expr function | Yann Herklotz | 2019-01-19 | 1 | -13/+16 |
| * | Add examples and data to tar file | Yann Herklotz | 2019-01-19 | 1 | -0/+2 |
| * | Remove shell from code blocks to remove random highlighting | Yann Herklotz | 2019-01-19 | 1 | -4/+4 |
| * | Remove code tags for links | Yann Herklotz | 2019-01-19 | 1 | -2/+2 |
| * | Add some documentation to main README | Yann Herklotz | 2019-01-19 | 1 | -0/+39 |
| * | Separate the lines of the simple example | Yann Herklotz | 2019-01-19 | 1 | -1/+2 |
| * | Swap the exports for the types of the AST | Yann Herklotz | 2019-01-19 | 1 | -2/+2 |
| * | Inline the timeout function | Yann Herklotz | 2019-01-19 | 1 | -0/+2 |
 |
index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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