| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Prettify files | Yann Herklotz | 2019-01-20 | 9 | -55/+117 |
| * | Add sby config | Yann Herklotz | 2019-01-20 | 1 | -5/+45 |
| * | Fix unit test and cabal file | Yann Herklotz | 2019-01-20 | 2 | -2/+1 |
| * | Add internal simulator module | Yann Herklotz | 2019-01-20 | 1 | -2/+3 |
| * | Add template file | Yann Herklotz | 2019-01-20 | 4 | -47/+72 |
| * | Rename moduleId to modId | Yann Herklotz | 2019-01-20 | 9 | -25/+39 |
| * | Reformat with stylish-haskell | Yann Herklotz | 2019-01-19 | 17 | -109/+90 |
| * | Add .hlint.yaml | Yann Herklotz | 2019-01-19 | 1 | -0/+60 |
| * | Add hlint changes | Yann Herklotz | 2019-01-19 | 3 | -4/+3 |
| * | Set column to 100 | Yann Herklotz | 2019-01-19 | 9 | -83/+31 |
| * | Add brittany formatting instead of stylish-haskell | Yann Herklotz | 2019-01-19 | 17 | -290/+387 |
| * | Small improvement to stmnt and expr function | Yann Herklotz | 2019-01-19 | 1 | -13/+16 |
| * | Add examples and data to tar file | Yann Herklotz | 2019-01-19 | 1 | -0/+2 |
| * | Remove shell from code blocks to remove random highlighting | Yann Herklotz | 2019-01-19 | 1 | -4/+4 |
| * | Remove code tags for links | Yann Herklotz | 2019-01-19 | 1 | -2/+2 |
| * | Add some documentation to main README | Yann Herklotz | 2019-01-19 | 1 | -0/+39 |
| * | Separate the lines of the simple example | Yann Herklotz | 2019-01-19 | 1 | -1/+2 |
| * | Swap the exports for the types of the AST | Yann Herklotz | 2019-01-19 | 1 | -2/+2 |
| * | Inline the timeout function | Yann Herklotz | 2019-01-19 | 1 | -0/+2 |
| * | Print absolute value of hash | Yann Herklotz | 2019-01-19 | 1 | -1/+1 |
| * | Add data folder with extra modules | Yann Herklotz | 2019-01-19 | 4 | -0/+418 |
| * | Fix all the warnings | Yann Herklotz | 2019-01-10 | 8 | -47/+37 |
| * | Add documentation in AST | Yann Herklotz | 2019-01-10 | 1 | -15/+28 |
| * | Fix documentation error | Yann Herklotz | 2019-01-10 | 1 | -1/+1 |
| * | Add explicit exports | Yann Herklotz | 2019-01-10 | 1 | -24/+55 |
| * | Fix warnings | Yann Herklotz | 2019-01-10 | 4 | -51/+38 |
| * | Remove Arbitrary from main module | Yann Herklotz | 2019-01-10 | 1 | -2/+0 |
| * | Derive as many properties as possible | Yann Herklotz | 2019-01-10 | 1 | -30/+21 |
| * | Fix some imports | Yann Herklotz | 2019-01-10 | 1 | -53/+14 |
| * | Add render to test | Yann Herklotz | 2019-01-10 | 1 | -3/+3 |
| * | Remove arbitrary from file list | Yann Herklotz | 2019-01-10 | 1 | -1/+0 |
| * | Remove Arbitrary.hs | Yann Herklotz | 2019-01-10 | 1 | -70/+0 |
| * | Fix warnings | Yann Herklotz | 2019-01-10 | 3 | -44/+13 |
| * | Update lts version | Yann Herklotz | 2019-01-10 | 2 | -12/+9 |
| * | Rename remaining modules | Yann Herklotz | 2019-01-10 | 9 | -230/+116 |
| * | Rename files out of the module | Yann Herklotz | 2019-01-10 | 19 | -0/+0 |
| * | Rename module names so that I can move them | Yann Herklotz | 2019-01-10 | 15 | -183/+315 |
| * | Move tests to test | Yann Herklotz | 2019-01-09 | 5 | -0/+0 |
| * | Add doctest-discover | Yann Herklotz | 2019-01-09 | 3 | -6/+10 |
| * | Add dependencies for hoogle support | Yann Herklotz | 2019-01-09 | 1 | -0/+4 |
| * | Add show instance to Identifier | Yann Herklotz | 2019-01-09 | 1 | -4/+8 |
| * | Fix Xst synthesis | Yann Herklotz | 2019-01-09 | 1 | -5/+11 |
| * | Small improvements to Icarus | Yann Herklotz | 2019-01-09 | 1 | -7/+12 |
| * | [Fix #19] Add support for equivalence checking | Yann Herklotz | 2019-01-09 | 1 | -7/+42 |
| * | [Fix #20] Add more examples and finish makeTop | Yann Herklotz | 2019-01-09 | 1 | -0/+31 |
| * | Change to timeout to support FilePath | Yann Herklotz | 2019-01-09 | 1 | -4/+4 |
| * | Make generated wires longer | Yann Herklotz | 2019-01-09 | 1 | -3/+5 |
| * | Adding more examples to main | Yann Herklotz | 2019-01-09 | 1 | -2/+9 |
| * | Remove Test.hs from build | Yann Herklotz | 2019-01-06 | 1 | -11/+2 |
| * | remove Test.hs, will all be in Main.hs | Yann Herklotz | 2019-01-06 | 1 | -19/+0 |
 |
index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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