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* Back to minimalYann Herklotz2018-12-291-0/+1
* Remove language specification as it is somehow slowerYann Herklotz2018-12-291-1/+0
* Triggering travis againYann Herklotz2018-12-290-0/+0
* Minimal language addedYann Herklotz2018-12-291-0/+1
* Add link to READMEYann Herklotz2018-12-292-2/+2
* Add more info to READMEYann Herklotz2018-12-291-3/+8
* Remove useless dependenciesYann Herklotz2018-12-291-5/+4
* Add badgeYann Herklotz2018-12-291-0/+3
* Downgrading ghcYann Herklotz2018-12-291-2/+2
* Trigger travisYann Herklotz2018-12-290-0/+0
* Add travis.yml fileYann Herklotz2018-12-291-0/+24
* Make generation more controlledYann Herklotz2018-12-292-8/+10
* Rearrange instancesYann Herklotz2018-12-291-5/+5
* Changes to the APIYann Herklotz2018-12-296-43/+64
* Add simulator codeYann Herklotz2018-12-293-8/+24
* Fix documentation and copyrightYann Herklotz2018-12-2818-54/+54
* Fix license againYann Herklotz2018-12-281-20/+19
* Another fix to copyrightYann Herklotz2018-12-281-1/+1
* Fix copyright noticeYann Herklotz2018-12-281-1/+1
* Add simulator moduleYann Herklotz2018-12-285-0/+215
* Fix imports and cabal fileYann Herklotz2018-12-285-24/+29
* Move verilog files into specific moduleYann Herklotz2018-12-284-21/+104
* Add executable for YosysYann Herklotz2018-12-281-0/+1
* Edit mainYann Herklotz2018-12-281-3/+3
* Add instantiation functionYann Herklotz2018-12-271-2/+7
* Remove OverloadedStrings in favour of declaration in moduleYann Herklotz2018-12-277-14/+1
* Add another example for declarations in verilogYann Herklotz2018-12-271-0/+31
* Add yosys shell scriptYann Herklotz2018-12-272-2/+32
* Generate completely random verilogYann Herklotz2018-12-271-3/+5
* Format fixesYann Herklotz2018-12-271-20/+20
* Small style changeYann Herklotz2018-12-271-1/+1
* Improve expression and statement generationYann Herklotz2018-12-271-20/+96
* Fix tests with new changesYann Herklotz2018-12-271-1/+1
* Fix main and improve speed of run scriptYann Herklotz2018-12-252-2/+3
* Add documentation to main moduleYann Herklotz2018-12-251-0/+13
* Add code generation for new typesYann Herklotz2018-12-251-20/+130
* Type fixesYann Herklotz2018-12-251-7/+8
* Rename Node to IntYann Herklotz2018-12-251-1/+1
* [Close #10, Fix #12] Add Mutations for wiresYann Herklotz2018-12-251-7/+13
* Add more typesYann Herklotz2018-12-251-41/+181
* Fix tests with ContAssignYann Herklotz2018-12-251-1/+1
* Add Helpers.hsYann Herklotz2018-12-252-0/+76
* Fix nesting, generation broken for nested groupsYann Herklotz2018-12-231-3/+17
* Add nesting to the SourceTextYann Herklotz2018-12-232-2/+19
* Add unit tests for the traversalYann Herklotz2018-12-234-8/+48
* [Fix #11] Implement the traversalYann Herklotz2018-12-231-18/+32
* Start implementing the nesting functionalityYann Herklotz2018-12-231-2/+23
* Fix running the simulationYann Herklotz2018-12-231-1/+3
* Derive `Eq` for the Verilog AST.Yann Herklotz2018-12-222-13/+14
* Add unimplemented nestId functionYann Herklotz2018-12-221-0/+4