verismith - Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.

	Commit message (Expand)	Author	Age	Files	Lines
*	Add new pretty printer with indentation	Yann Herklotz	2019-05-09	9	-219/+191
*	Add reduction strategy for modules	Yann Herklotz	2019-05-09	5	-16/+166
*	Add NFData to force evaluation of config file	Yann Herklotz	2019-05-09	10	-167/+102
*	Upgrade stack LTS version	Yann Herklotz	2019-05-09	1	-3/+3
*	Add supported simulators to readme	Yann Herklotz	2019-05-09	1	-0/+2
*	Fix unusable UNPACK	Yann Herklotz	2019-05-09	1	-1/+1
*	Add combinational and sequential logic support	Yann Herklotz	2019-05-09	3	-97/+55
*	Only show the seed	Yann Herklotz	2019-05-07	1	-3/+1
*	Add configuration options for all simulators	Yann Herklotz	2019-05-07	7	-66/+213
*	Add description field to Yosys	Yann Herklotz	2019-05-07	3	-14/+13
*	Use abc for verification	Yann Herklotz	2019-05-07	3	-8/+6
*	Create better command line output	Yann Herklotz	2019-05-07	3	-9/+16
*	Rename some functions to use nicer names	Yann Herklotz	2019-05-07	10	-55/+62
*	Add support for multiple modules	Yann Herklotz	2019-05-07	4	-11/+41
*	Fix a warning in cells_cyclone_v.v	Yann Herklotz	2019-05-06	1	-241/+241
*	Fix bug in Config.hs	Yann Herklotz	2019-05-06	1	-6/+6
*	Replace by the unisims model	Yann Herklotz	2019-05-06	1	-13/+7
*	[Fix #49] Add LDPE cell to xilinx	Yann Herklotz	2019-05-06	1	-24/+39
*	Support multiple reg assigns in if statements	Yann Herklotz	2019-05-06	10	-82/+110
*	Modify generation of statements to create more interesting ones	Yann Herklotz	2019-05-05	1	-16/+35
*	Format with brittany	Yann Herklotz	2019-05-05	7	-58/+91
*	Write config file with seed to the fuzz directory	Yann Herklotz	2019-05-05	2	-18/+21
*	Add seeds for reproducible runs	Yann Herklotz	2019-05-05	5	-46/+85
*	Add more reduction to tests	Yann Herklotz	2019-04-29	1	-2/+10
*	Add random bit selection for wires	Yann Herklotz	2019-04-26	6	-44/+89
*	Add --num command line option	Yann Herklotz	2019-04-25	1	-2/+11
*	Add time and date by default	Yann Herklotz	2019-04-24	2	-7/+20
*	Add documentation to Config.hs	Yann Herklotz	2019-04-23	2	-18/+130
*	Fix cells_xilinx_7.v LD and FD modules	Yann Herklotz	2019-04-23	1	-17/+0
*	Fix some errors in the templates	Yann Herklotz	2019-04-23	2	-0/+53
*	Fix XST Synthesis	Yann Herklotz	2019-04-23	1	-1/+1
*	Add simulator support to the config file	Yann Herklotz	2019-04-23	2	-179/+101
*	Formatting files and add result type to front end	Yann Herklotz	2019-04-23	6	-8/+15
*	Fix code generation for always blocks with or	Yann Herklotz	2019-04-23	1	-3/+3
*	Fine tune the generation	Yann Herklotz	2019-04-23	1	-15/+13
*	Add Report type	Yann Herklotz	2019-04-23	3	-1/+172
*	Add event list generation for always blocks	Yann Herklotz	2019-04-23	3	-73/+4
*	Add support for more event lists	Yann Herklotz	2019-04-21	4	-11/+74
*	Add new modules to fix Quartus equivalence check	Yann Herklotz	2019-04-21	2	-1/+55
*	Add helper functions to execute fuzzing multiple times	Yann Herklotz	2019-04-19	2	-11/+26
*	Move --pedantic flag to the end	Yann Herklotz	2019-04-19	1	-1/+1
*	Fix compiling on CI	Yann Herklotz	2019-04-19	2	-2/+7
*	Fix some suggestions in Result.hs	Yann Herklotz	2019-04-19	1	-5/+2
*	Equivalence test now running	Yann Herklotz	2019-04-19	1	-2/+1
*	Extend ResultT and Result with more instances	Yann Herklotz	2019-04-19	3	-9/+49
*	Add output information to Type	Yann Herklotz	2019-04-18	8	-82/+95
*	Add output path to each simulator	Yann Herklotz	2019-04-18	6	-50/+121
*	Use new fuzzing technique instead of the old function	Yann Herklotz	2019-04-17	5	-28/+36
*	Reduce the wire size as Quartus was crashing	Yann Herklotz	2019-04-17	1	-1/+9
*	Extend property tests to ResultT	Yann Herklotz	2019-04-17	1	-25/+21