verismith - Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.

	Commit message (Expand)	Author	Age	Files	Lines
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*	Add AST generation	Yann Herklotz	2018-12-15	1	-0/+47
*	Add qualified imports	Yann Herklotz	2018-12-15	1	-13/+12
*	Rename types to circuit	Yann Herklotz	2018-12-15	1	-1/+15
*	Add rerun script	Yann Herklotz	2018-12-04	1	-0/+7
*	[Fix #1] Fix the negative number generation	Yann Herklotz	2018-12-04	2	-2/+5
*	Add newline to test	Yann Herklotz	2018-12-04	1	-0/+1
*	Add quickcheck to main	Yann Herklotz	2018-12-04	2	-0/+4
*	[Fix #8] Add Circuit newtype	Yann Herklotz	2018-12-02	1	-0/+3
*	Fix typo	Yann Herklotz	2018-12-01	1	-1/+1
*	Add newline after module declaration	Yann Herklotz	2018-12-01	1	-1/+1
*	Fix the code generation	Yann Herklotz	2018-12-01	1	-1/+13
*	Add all arbitrary instances and fix identifier	Yann Herklotz	2018-12-01	1	-15/+65
*	Add more code to the shared code	Yann Herklotz	2018-12-01	2	-15/+15
*	Add modport helper function	Yann Herklotz	2018-12-01	1	-0/+3
*	Add more code generation for expressions	Yann Herklotz	2018-12-01	1	-0/+40
*	Add missing modules to main library	Yann Herklotz	2018-12-01	1	-0/+2
*	Add internal shared module	Yann Herklotz	2018-12-01	1	-0/+4
*	Move generation to new location	Yann Herklotz	2018-12-01	2	-59/+79
*	[lint] Remove unnecessary '$'	Yann Herklotz	2018-12-01	1	-1/+1
*	Fix data types and apply more hlint suggestions	Yann Herklotz	2018-12-01	1	-8/+6
*	Add new modules	Yann Herklotz	2018-12-01	1	-1/+3
*	Apply HLint rules	Yann Herklotz	2018-12-01	1	-1/+1
*	Add helper methods	Yann Herklotz	2018-12-01	1	-6/+15
*	Add assignment to ModuleItem	Yann Herklotz	2018-11-30	1	-3/+2
*	Add more types	Yann Herklotz	2018-11-30	1	-12/+25
*	Make the test case clearer	Yann Herklotz	2018-11-30	1	-3/+4
*	Add tests to the cabal file	Yann Herklotz	2018-11-30	1	-0/+3
*	Fix type issue in main	Yann Herklotz	2018-11-30	2	-6/+11
*	Add first property test	Yann Herklotz	2018-11-30	3	-12/+36
*	Make simple test pass	Yann Herklotz	2018-11-30	1	-1/+1
*	Rename the Test file	Yann Herklotz	2018-11-30	2	-1/+1
*	Reformat the main file and upgrade lts	Yann Herklotz	2018-11-30	3	-14/+15
*	Restructure and add tests	Yann Herklotz	2018-11-30	3	-9/+34
*	Add lens library and extend types for AST	Yann Herklotz	2018-11-30	2	-8/+67
*	Add AST to the exported modules	Yann Herklotz	2018-11-30	1	-0/+3
*	Add some simplifications (map -> fmap)	Yann Herklotz	2018-11-29	1	-5/+6
*	Add Verilog AST	Yann Herklotz	2018-11-29	1	-0/+13
*	Improve generation	Yann Herklotz	2018-11-16	1	-15/+15
*	Basic generation with errors	Yann Herklotz	2018-11-16	3	-6/+24
*	Add .gitignore	Yann Herklotz	2018-11-16	1	-0/+5
*	Remove Nor and Nand from types	Yann Herklotz	2018-11-16	1	-4/+2
*	Format and remove unnecessary declarations	Yann Herklotz	2018-11-16	1	-6/+3
*	Add statements to the Verilog module	Yann Herklotz	2018-11-16	1	-12/+24
*	Better format for the Verilog file	Yann Herklotz	2018-11-16	1	-6/+6
*	Add style to the files	Yann Herklotz	2018-11-14	7	-26/+25
*	Add testbench to the end	Yann Herklotz	2018-11-09	1	-1/+1
*	Generate some Verilog code from graph	Yann Herklotz	2018-11-09	2	-9/+38
*	Random generation of DAG	Yann Herklotz	2018-11-09	4	-34/+46
*	Improve cabal module	Yann Herklotz	2018-11-09	1	-1/+19
*	Add main module	Yann Herklotz	2018-11-09	1	-0/+13