verismith - Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.

	Commit message (Collapse)	Author	Age	Files	Lines
*	Add data folder with extra modules	Yann Herklotz	2019-01-19	1	-0/+38
	These modules are required for comparing modules that are generated by synthesising in different simulators, as they will each synthesise to specific hardware with assumptions on what is available