| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Fix cyclone_v cell declaration | Yann Herklotz | 2019-06-02 | 1 | -46/+12 |
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| * | Fix a warning in cells_cyclone_v.v | Yann Herklotz | 2019-05-06 | 1 | -241/+241 |
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| * | Add new modules to fix Quartus equivalence check | Yann Herklotz | 2019-04-21 | 1 | -1/+54 |
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| * | Add data folder with extra modules | Yann Herklotz | 2019-01-19 | 1 | -0/+238 |
| These modules are required for comparing modules that are generated by synthesising in different simulators, as they will each synthesise to specific hardware with assumptions on what is available | |||||
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index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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