| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [Fix #49] Add LDPE cell to xilinx | Yann Herklotz | 2019-05-06 | 1 | -24/+39 |
| * | Fix cells_xilinx_7.v LD and FD modules | Yann Herklotz | 2019-04-23 | 1 | -17/+0 |
| * | Fix some errors in the templates | Yann Herklotz | 2019-04-23 | 1 | -0/+52 |
| * | Add new modules to fix Quartus equivalence check | Yann Herklotz | 2019-04-21 | 1 | -1/+54 |
| * | Add more primitives to data/ | Yann Herklotz | 2019-04-06 | 2 | -7/+77 |
| * | Add missing modules when using always blocks | Yann Herklotz | 2019-04-03 | 2 | -75/+108 |
| * | Add data folder with extra modules | Yann Herklotz | 2019-01-19 | 4 | -0/+418 |
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index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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