Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | Add some simplifications (map -> fmap) | Yann Herklotz | 2018-11-29 | 1 | -5/+6 |
* | Improve generation | Yann Herklotz | 2018-11-16 | 1 | -15/+15 |
* | Basic generation with errors | Yann Herklotz | 2018-11-16 | 1 | -4/+22 |
* | Add statements to the Verilog module | Yann Herklotz | 2018-11-16 | 1 | -12/+24 |
* | Add style to the files | Yann Herklotz | 2018-11-14 | 1 | -4/+3 |
* | Add testbench to the end | Yann Herklotz | 2018-11-09 | 1 | -1/+1 |
* | Generate some Verilog code from graph | Yann Herklotz | 2018-11-09 | 1 | -0/+32 |
* | Random generation of DAG | Yann Herklotz | 2018-11-09 | 1 | -1/+1 |
* | Add initial module files | Yann Herklotz | 2018-11-09 | 1 | -0/+1 |