verismith - Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.

	Commit message (Collapse)	Author	Age	Files	Lines
*	Fix imports and cabal file	Yann Herklotz	2018-12-28	1	-3/+3
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*	Remove OverloadedStrings in favour of declaration in module	Yann Herklotz	2018-12-27	2	-4/+0
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*	Small style change	Yann Herklotz	2018-12-27	1	-1/+1
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*	Type fixes	Yann Herklotz	2018-12-25	1	-7/+8
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*	Format ASTGen	Yann Herklotz	2018-12-22	1	-6/+3
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*	[Fix #2] Add generation of AST from Circuit	Yann Herklotz	2018-12-22	1	-8/+21
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*	Add more functions to the code generation	Yann Herklotz	2018-12-22	2	-25/+21
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*	Add more AST generation	Yann Herklotz	2018-12-20	1	-1/+19
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*	Fix documentation	Yann Herklotz	2018-12-15	2	-2/+32
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*	Add AST generation	Yann Herklotz	2018-12-15	1	-0/+47
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*	Add more code to the shared code	Yann Herklotz	2018-12-01	1	-15/+5
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*	Move generation to new location	Yann Herklotz	2018-12-01	1	-0/+63
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*	[lint] Remove unnecessary '$'	Yann Herklotz	2018-12-01	1	-1/+1
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*	Fix type issue in main	Yann Herklotz	2018-11-30	1	-5/+10
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*	Basic generation with errors	Yann Herklotz	2018-11-16	1	-1/+1
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*	Format and remove unnecessary declarations	Yann Herklotz	2018-11-16	1	-6/+3
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*	Add style to the files	Yann Herklotz	2018-11-14	1	-4/+6
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*	Random generation of DAG	Yann Herklotz	2018-11-09	1	-13/+26
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*	Add initial module files	Yann Herklotz	2018-11-09	1	-0/+13