| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Fix type issue in main | Yann Herklotz | 2018-11-30 | 1 | -5/+10 |
| * | Basic generation with errors | Yann Herklotz | 2018-11-16 | 1 | -1/+1 |
| * | Format and remove unnecessary declarations | Yann Herklotz | 2018-11-16 | 1 | -6/+3 |
| * | Add style to the files | Yann Herklotz | 2018-11-14 | 1 | -4/+6 |
| * | Random generation of DAG | Yann Herklotz | 2018-11-09 | 1 | -13/+26 |
| * | Add initial module files | Yann Herklotz | 2018-11-09 | 1 | -0/+13 |
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index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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