| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Rename files out of the module | Yann Herklotz | 2019-01-10 | 4 | -268/+0 |
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| * | Rename module names so that I can move them | Yann Herklotz | 2019-01-10 | 4 | -55/+42 |
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| * | Fix Xst synthesis | Yann Herklotz | 2019-01-09 | 1 | -5/+11 |
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| * | Small improvements to Icarus | Yann Herklotz | 2019-01-09 | 1 | -7/+12 |
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| * | [Fix #19] Add support for equivalence checking | Yann Herklotz | 2019-01-09 | 1 | -7/+42 |
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| * | Change to timeout to support FilePath | Yann Herklotz | 2019-01-09 | 1 | -4/+4 |
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| * | Finish the testbenck for Icarus | Yann Herklotz | 2019-01-02 | 1 | -2/+18 |
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| * | Add bsToI function | Yann Herklotz | 2019-01-01 | 1 | -5/+8 |
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| * | Fix linting warnings | Yann Herklotz | 2019-01-01 | 3 | -5/+3 |
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| * | Use Monoid Statement instance to make code more concise | Yann Herklotz | 2019-01-01 | 1 | -5/+3 |
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| * | Adding code to Icarus | Yann Herklotz | 2018-12-31 | 1 | -3/+15 |
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| * | Add simulator code | Yann Herklotz | 2018-12-29 | 3 | -8/+24 |
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| * | Fix documentation and copyright | Yann Herklotz | 2018-12-28 | 4 | -12/+12 |
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| * | Add simulator module | Yann Herklotz | 2018-12-28 | 4 | -0/+192 |
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index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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