verismith - Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.

	Commit message (Collapse)	Author	Age	Files	Lines
*	Rename files out of the module	Yann Herklotz	2019-01-10	1	-148/+0
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*	Rename module names so that I can move them	Yann Herklotz	2019-01-10	1	-8/+8
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*	[Fix #20] Add more examples and finish makeTop	Yann Herklotz	2019-01-09	1	-0/+31
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*	Fix linting warnings	Yann Herklotz	2019-01-01	1	-2/+2
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*	Add show instance and add concat to reglval	Yann Herklotz	2018-12-31	1	-2/+2
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*	Large refactor	Yann Herklotz	2018-12-31	1	-8/+8
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*	Finish module instantiation	Yann Herklotz	2018-12-31	1	-5/+10
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*	Add direction to Decl and add doctest	Yann Herklotz	2018-12-31	1	-5/+17
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*	[Fix #17] Add size to ports	Yann Herklotz	2018-12-31	1	-2/+2
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*	Add doctest test	Yann Herklotz	2018-12-31	1	-0/+8
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*	[Fix #13, Fix #15] Fix type errors and add inst functions	Yann Herklotz	2018-12-30	1	-8/+11
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*	[Fix #14] Add size to Port type	Yann Herklotz	2018-12-30	1	-0/+5
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*	Changes to the API	Yann Herklotz	2018-12-29	1	-1/+5
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*	Fix documentation and copyright	Yann Herklotz	2018-12-28	1	-3/+3
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*	Move verilog files into specific module	Yann Herklotz	2018-12-28	1	-0/+80