Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | Large refactor | Yann Herklotz | 2018-12-31 | 4 | -317/+138 |
* | Finish module instantiation | Yann Herklotz | 2018-12-31 | 2 | -5/+16 |
* | Add direction to Decl and add doctest | Yann Herklotz | 2018-12-31 | 4 | -11/+26 |
* | [Fix #17] Add size to ports | Yann Herklotz | 2018-12-31 | 2 | -5/+13 |
* | Add doctest test | Yann Herklotz | 2018-12-31 | 1 | -0/+8 |
* | [Fix #13, Fix #15] Fix type errors and add inst functions | Yann Herklotz | 2018-12-30 | 3 | -13/+16 |
* | Change modPort type from Maybe to List | Yann Herklotz | 2018-12-30 | 1 | -1/+1 |
* | [Fix #14] Add size to Port type | Yann Herklotz | 2018-12-30 | 3 | -12/+21 |
* | Move helper functions | Yann Herklotz | 2018-12-30 | 1 | -0/+76 |
* | Fix verilog output for output port | Yann Herklotz | 2018-12-29 | 1 | -1/+1 |
* | Make generation more controlled | Yann Herklotz | 2018-12-29 | 1 | -2/+4 |
* | Rearrange instances | Yann Herklotz | 2018-12-29 | 1 | -5/+5 |
* | Changes to the API | Yann Herklotz | 2018-12-29 | 3 | -23/+33 |
* | Fix documentation and copyright | Yann Herklotz | 2018-12-28 | 3 | -9/+9 |
* | Move verilog files into specific module | Yann Herklotz | 2018-12-28 | 3 | -0/+751 |