verismith - Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.

	Commit message (Expand)	Author	Age	Files	Lines
*	Formatting	Yann Herklotz	2019-01-01	1	-3/+3
*	Remove empty statement and Monoid instance	Yann Herklotz	2019-01-01	1	-4/+0
*	Fix Semigroup instances	Yann Herklotz	2019-01-01	1	-4/+8
*	Add documentation	Yann Herklotz	2019-01-01	1	-0/+10
*	Add string instance to expression	Yann Herklotz	2019-01-01	1	-12/+42
*	Add missing case in function	Yann Herklotz	2018-12-31	1	-0/+2
*	Add show instance and add concat to reglval	Yann Herklotz	2018-12-31	4	-42/+88
*	Fix build errors	Yann Herklotz	2018-12-31	1	-0/+1
*	Remove sep and fromList in favour of fold	Yann Herklotz	2018-12-31	1	-3/+3
*	Separate arbitrary from types	Yann Herklotz	2018-12-31	1	-0/+184
*	Large refactor	Yann Herklotz	2018-12-31	4	-317/+138
*	Finish module instantiation	Yann Herklotz	2018-12-31	2	-5/+16
*	Add direction to Decl and add doctest	Yann Herklotz	2018-12-31	4	-11/+26
*	[Fix #17] Add size to ports	Yann Herklotz	2018-12-31	2	-5/+13
*	Add doctest test	Yann Herklotz	2018-12-31	1	-0/+8
*	[Fix #13, Fix #15] Fix type errors and add inst functions	Yann Herklotz	2018-12-30	3	-13/+16
*	Change modPort type from Maybe to List	Yann Herklotz	2018-12-30	1	-1/+1
*	[Fix #14] Add size to Port type	Yann Herklotz	2018-12-30	3	-12/+21
*	Move helper functions	Yann Herklotz	2018-12-30	1	-0/+76
*	Fix verilog output for output port	Yann Herklotz	2018-12-29	1	-1/+1
*	Make generation more controlled	Yann Herklotz	2018-12-29	1	-2/+4
*	Rearrange instances	Yann Herklotz	2018-12-29	1	-5/+5
*	Changes to the API	Yann Herklotz	2018-12-29	3	-23/+33
*	Fix documentation and copyright	Yann Herklotz	2018-12-28	3	-9/+9
*	Move verilog files into specific module	Yann Herklotz	2018-12-28	3	-0/+751