Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | Add more types | Yann Herklotz | 2018-12-25 | 1 | -41/+181 |
* | [Fix #11] Implement the traversal | Yann Herklotz | 2018-12-23 | 1 | -18/+32 |
* | Derive `Eq` for the Verilog AST. | Yann Herklotz | 2018-12-22 | 1 | -13/+13 |
* | [Fix #2] Add generation of AST from Circuit | Yann Herklotz | 2018-12-22 | 1 | -1/+1 |
* | Fix documentation | Yann Herklotz | 2018-12-15 | 1 | -13/+44 |
* | [Fix #1] Fix the negative number generation | Yann Herklotz | 2018-12-04 | 1 | -1/+1 |
* | Add all arbitrary instances and fix identifier | Yann Herklotz | 2018-12-01 | 1 | -15/+65 |
* | Add modport helper function | Yann Herklotz | 2018-12-01 | 1 | -0/+3 |
* | Fix data types and apply more hlint suggestions | Yann Herklotz | 2018-12-01 | 1 | -8/+6 |
* | Add helper methods | Yann Herklotz | 2018-12-01 | 1 | -6/+15 |
* | Add assignment to ModuleItem | Yann Herklotz | 2018-11-30 | 1 | -3/+2 |
* | Add more types | Yann Herklotz | 2018-11-30 | 1 | -12/+25 |
* | Add lens library and extend types for AST | Yann Herklotz | 2018-11-30 | 1 | -5/+65 |
* | Add Verilog AST | Yann Herklotz | 2018-11-29 | 1 | -0/+13 |