Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | Remove Nor and Nand from types | Yann Herklotz | 2018-11-16 | 1 | -4/+2 |
* | Format and remove unnecessary declarations | Yann Herklotz | 2018-11-16 | 1 | -6/+3 |
* | Add statements to the Verilog module | Yann Herklotz | 2018-11-16 | 1 | -12/+24 |
* | Add style to the files | Yann Herklotz | 2018-11-14 | 4 | -14/+15 |
* | Add testbench to the end | Yann Herklotz | 2018-11-09 | 1 | -1/+1 |
* | Generate some Verilog code from graph | Yann Herklotz | 2018-11-09 | 1 | -0/+32 |
* | Random generation of DAG | Yann Herklotz | 2018-11-09 | 3 | -16/+42 |
* | Add main module | Yann Herklotz | 2018-11-09 | 1 | -0/+13 |
* | Add initial module files | Yann Herklotz | 2018-11-09 | 3 | -0/+22 |