| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [Fix #34, Fix #36] Add Ord instance to AST | Yann Herklotz Grave | 2019-03-01 | 1 | -49/+60 |
| * | Add Ord to AST and fix reduction function | Yann Herklotz Grave | 2019-02-26 | 1 | -22/+22 |
| * | Reformat using brittany | Yann Herklotz Grave | 2019-02-25 | 1 | -6/+9 |
| * | Indent by 4 | Yann Herklotz Grave | 2019-02-17 | 1 | -117/+116 |
| * | Brittany formatting | Yann Herklotz Grave | 2019-02-17 | 1 | -27/+21 |
| * | Change Port type, adding signed info | Yann Herklotz Grave | 2019-02-16 | 1 | -11/+11 |
| * | Take out non synthesisable comparison | Yann Herklotz Grave | 2019-02-15 | 1 | -2/+2 |
| * | Fix all warnings | Yann Herklotz Grave | 2019-02-15 | 1 | -2/+3 |
| * | Add Data derivations to AST and Plated instance to Expr | Yann Herklotz | 2019-02-08 | 1 | -26/+42 |
| * | Remove divide and mod from the generator list | Yann Herklotz | 2019-02-07 | 1 | -2/+2 |
| * | Try to add logging | Yann Herklotz | 2019-02-02 | 1 | -1/+1 |
| * | Add case for empty context | Yann Herklotz | 2019-02-02 | 1 | -0/+5 |
| * | Fix imports | Yann Herklotz | 2019-02-01 | 1 | -2/+2 |
| * | More restructuring | Yann Herklotz | 2019-02-01 | 1 | -0/+564 |
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index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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