| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Format with brittany | Yann Herklotz | 2019-05-05 | 1 | -1/+1 |
| * | Add seeds for reproducible runs | Yann Herklotz | 2019-05-05 | 1 | -9/+11 |
| * | Add random bit selection for wires | Yann Herklotz | 2019-04-26 | 1 | -10/+15 |
| * | Add documentation to Config.hs | Yann Herklotz | 2019-04-23 | 1 | -16/+128 |
| * | Add simulator support to the config file | Yann Herklotz | 2019-04-23 | 1 | -17/+55 |
| * | Add support for more event lists | Yann Herklotz | 2019-04-21 | 1 | -4/+33 |
| * | Use new fuzzing technique instead of the old function | Yann Herklotz | 2019-04-17 | 1 | -1/+1 |
| * | Remove blocking assignment from Generation | Yann Herklotz | 2019-04-14 | 1 | -1/+1 |
| * | Add for loop to design | Yann Herklotz | 2019-04-12 | 1 | -1/+5 |
| * | Fix the generation of modules and add initialisation | Yann Herklotz | 2019-04-10 | 1 | -64/+67 |
| * | Add probabilities to generation of expressions | Yann Herklotz | 2019-04-09 | 1 | -1/+1 |
| * | Add more configuration options | Yann Herklotz | 2019-04-09 | 1 | -31/+125 |
| * | Fix infinite loop in state based generation | Yann Herklotz | 2019-04-03 | 1 | -1/+1 |
| * | Apply brittany to modified modules | Yann Herklotz | 2019-04-03 | 1 | -6/+11 |
| * | Fix hlint hints | Yann Herklotz | 2019-04-02 | 1 | -1/+1 |
| * | Add more configuration options and small fix | Yann Herklotz | 2019-04-02 | 1 | -10/+27 |
| * | Add conditionals to config | Yann Herklotz | 2019-04-02 | 1 | -1/+5 |
| * | Change license name | Yann Herklotz | 2019-03-30 | 1 | -1/+1 |
| * | Add proper register generation | Yann Herklotz Grave | 2019-03-07 | 1 | -1/+1 |
| * | Add more probabilities to config | Yann Herklotz Grave | 2019-03-06 | 1 | -23/+27 |
| * | Add more configuration options | Yann Herklotz Grave | 2019-03-06 | 1 | -6/+54 |
| * | Run formatting on Config.hs | Yann Herklotz Grave | 2019-03-04 | 1 | -6/+12 |
| * | Add toml configuration support for probabilities | Yann Herklotz Grave | 2019-03-04 | 1 | -0/+57 |
 |
index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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